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[1] Liang Bangli, Wang Zhigong, Tian Jun, Feng JunXia Chunxiao, et al. A 0.6 μm CMOS bandgap voltage reference circuit [J]. Journal of Southeast University (English Edition), 2003, 19 (3): 221-224. [doi:10.3969/j.issn.1003-7985.2003.03.004]
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A 0.6 μm CMOS bandgap voltage reference circuit()
一种 0.6 μm CMOS带隙参考电压源
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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
19
Issue:
2003 3
Page:
221-224
Research Field:
Electronic Science and Engineering
Publishing date:
2003-09-30

Info

Title:
A 0.6 μm CMOS bandgap voltage reference circuit
一种 0.6 μm CMOS带隙参考电压源
Author(s):
Liang Bangli1;  Wang Zhigong1;  Tian Jun1;  2;  Feng Jun1Xia Chunxiao1;  Hu Yan1;  Zhang Li1;  Xiong Mingzhen1
1Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
2Physics Department, Nanjing University, Nanjing 210093, China
梁帮立1;  王志功1;  田俊1;  2;  冯军1;  夏春晓1;  胡艳1;  张丽1;  熊明珍1
1东南大学射频与光电集成电路研究所, 南京 210096; 2南京大学物理系, 南京 210093
Keywords:
CMOS;  mutual compensation;  mobility and threshold voltage temperature effects
CMOS;  相互补偿;  迁移率和阈值电压温度效应
PACS:
TN722
DOI:
10.3969/j.issn.1003-7985.2003.03.004
Abstract:
On the basis of mutual compensation of mobility and threshold voltage temperature effects, a stable CMOS band-gap voltage reference circuit was designed and fabricated in CSMC-HJ 0.6 μm CMOS technology. Operating from 0 to 85 ℃ under a supply voltage ranging from 4.5 to 5.5 V, the voltage reference circuit offers an output reference voltage ranging from 1.122 to 1.176 V and a voltage variation less than ±3.70%. The chip size including bonding pads is only 0.4 mm×0.4 mm and the power dissipation falls inside the scope of 28.3 to 48.8 mW operating at a supply voltage of 4.5 to 5.5 V.
利用CMOS晶体管迁移率和阈值电压温度效应相互补偿的原理, 采用CSMC-HJ 0.6 μm CMOS技术设计了一种稳定的带隙参考电压源, 该带隙参考电压源可以在0~85 ℃、电源电压 4.5~5.5 V的范围内正常工作, 输出参考电压为1.122~1.176 V, 输出参考电压浮动比例小于±3.70%. 包括键合用的焊盘在内, 芯片的总面积仅为0.4 mm×0.4 mm, 当电源电压在4.5~5.5V范围内变化时, 电路总的功率消耗在28.3~48.8 mW 之间浮动.

References:

[1] Filanovsky I M, Allam A. Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits[J]. IEEE J Solid-State Circuits, 2001, 48(7): 876-884.
[2] Klaassen F M, Hes W. On the temperature coefficient of the MOSFET threshold voltage [J]. Solid State Electron, 1986, 29(8): 787-789.
[3] Manku T, Wang Y. Temperature-independent output voltage generated by threshold voltage of an NMOS transistor[J]. Electron Lett, 1995, 31(6): 935-936.
[4] Shoucair F S. Design considerations in high-temperature analog CMOS integrated circuits [J]. IEEE Trans Comp, Hybrids, Manufacture, Technology, 1986, 9(3): 242-251.
[5] Filanovsky I M. Input-free VTP and -VTN extractor circuits realized on the same chip[J]. Analog Integrated Circuits Signal Process, 1999, 19(2): 151-157.

Memo

Memo:
Biographies: Liang Bangli(1974—), male, engineer; Wang Zhigong(corresponding author), male, doctor, professor, zgwang@seu.edu.cn.
Last Update: 2003-09-20