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[1] Wang Jianxin, Zhu En,. A high-throughput VLSI design for JPEG2000 9/7discrete wavelet transform [J]. Journal of Southeast University (English Edition), 2015, 31 (1): 19-24. [doi:10.3969/j.issn.1003-7985.2015.01.004]
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A high-throughput VLSI design for JPEG2000 9/7discrete wavelet transform()
一种高吞吐率JPEG2000 9/7离散小波变换VLSI设计
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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
31
Issue:
2015 1
Page:
19-24
Research Field:
Circuit and System
Publishing date:
2015-03-30

Info

Title:
A high-throughput VLSI design for JPEG2000 9/7discrete wavelet transform
一种高吞吐率JPEG2000 9/7离散小波变换VLSI设计
Author(s):
Wang Jianxin;  Zhu En
School of Information Science and Engineering, Southeast University, Nanjing 210096, China
王建新;  朱恩
东南大学信息科学与工程学院, 南京210096
Keywords:
JPEG2000;  flipping structure;  2D discrete wavelet transform(DWT);  9/7 DWT;  very large scale integration(VLSI)
JPEG2000;  翻转结构;  二维离散小波变换;  9/7离散小波变换;  VLSI
PACS:
TN47
DOI:
10.3969/j.issn.1003-7985.2015.01.004
Abstract:
To achieve high parallel computation of discrete wavelet transform(DWT)in JPEG2000, a high-throughput two-dimensional(2D)9/7 DWT very large scale integration(VLSI)design is proposed, in which the row processor is based on flipping structure. Due to the difference of the input data flow, the column processor is obtained by adding the input selector and data buffer to the row processor. Normalization steps in row and column DWT are combined to reduce the number of multipliers, and the rationality is verified. By rearranging the output of four-line row DWT with a multiplexer(MUX), the amount of data processed by each column processor becomes half, and the four-input/four-output architecture is implemented. For an image with the size of N×N, the computing time of one-level 2D 9/7 DWT is 0.25N2+1.5N clock cycles. The critical path delay is one multiplier delay, and only 5N internal memory is required. The results of post-route simulation on FPGA show that clock frequency reaches 136 MHz, and the throughput is 544 Msample/s, which satisfies the requirements of high-speed applications.
为提高JPEG2000系统中离散小波变换的计算并行度, 设计了一种高吞吐率二维9/7离散小波变换VLSI架构.其行变换核采用翻转结构, 并根据行列变换核输入数据流的差异, 在行变换核基础上增加输入选择器和数据缓存模块得到列变换核.对行列变换的归一化过程进行融合以节省乘法器, 并论证了其合理性.通过多路选择器重排4个行变换核的输出, 使每个列变换核处理的数据量减半, 实现四路输入、四路输出.对一幅N×N的灰度图像进行一层9/7小波变换, 计算时间为0.25N2+1.5N个周期, 关键路径延迟为1个乘法器延迟, 且只需5N存储空间.FPGA后仿真结果表明, 时钟频率可达136 MHz, 吞吐率达到544 Msample/s, 可以满足高速率应用的要求.

References:

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Memo

Memo:
Biographies: Wang Jianxin(1989—), male, graduate; Zhu En(corresponding author), male, doctor, professor, zhuenpro@seu.edu.cn.
Foundation item: The National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2014ZX03003007-009).
Citation: Wang Jianxin, Zhu En. A high-throughput VLSI design for JPEG2000 9/7 discrete wavelet transform[J].Journal of Southeast University(English Edition), 2015, 31(1):19-24.[doi:10.3969/j.issn.1003-7985.2015.01.004]
Last Update: 2015-03-20