[1] Liang Huaguo, Li Weidi, Xu Xiumin, Wang Haoyu, et al. A method to improve PUF reliability in FPGAs [J]. Journal of Southeast University (English Edition), 2018, 34 (1): 15-20. [doi:10.3969/j.issn.1003-7985.2018.01.003]

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A method to improve PUF reliability in FPGAs()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

34

Issue:

2018 1

Page:

15-20

Research Field:

Information and Communication Engineering

Publishing date:

2018-03-20

Info

Title:

A method to improve PUF reliability in FPGAs

Author(s):

Liang Huaguo;  Li Weidi;  Xu Xiumin;  Wang Haoyu

School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230000, China

Keywords:

field programmable gate array(FPGA);  physical unclonable function(PUF);  security;  ring oscillator(RO);  reliability

PACS:

TN918.91

DOI:

10.3969/j.issn.1003-7985.2018.01.003

Abstract:

Due to the impact of voltage, temperature and device aging, the traditional ring oscillator-based physical unclonable functions(RO-PUF)suffers from an unreliability issue, i.e., PUF output is subject to a constant change. To improve the reliability of the PUF, a stability test scheme related to the PUF mapping unit is proposed. The scheme uses ring oscillators with multiple complexity and various frequencies as sources of interference, which are placed near the PUF prototype circuit to interfere with it. By identifying and discarding unstable slices which lead to the instability of PUF, PUF reliability can be effectively improved. Experimental results show that surrounding logic circuits with multiple complexity and multiple frequencies can identify different unstable slices, and the higher the complexity, the more unstable slices are detected. Moreover, compared with newly published PUF literature, the PUF circuit possesses better statistical characteristic of randomness and lower resource consumption. With temperatures varying from 0 to 120 ℃ and voltage fluctuating between 0.85 and 1.2 V, its uniqueness and stability can achieve 49.78% and 98.00%, respectively, which makes it better for use in the field of security.

References:

[1] Gassend B, Clarke D, van Dijk M, et al. Silicon physical random functions[C]// Proceedings of the 9th ACM Conference on Computer and Communications Security. Washington, DC, USA, 2002: 148-160. DOI:10.1145/586131.586132.
[2] Suh G E, Devadas S. Physical unclonable functions for device authentication and secret key generation[C]//2007 44th ACM/IEEE Design Automation Conference. San Diego, CA, USA, 2007: 9-14. DOI:10.1109/dac.2007.375043.
[3] Herder C, Yu M D, Koushanfar F, et al. Physical unclonable functions and applications: A tutorial[J]. Proceedings of the IEEE, 2014, 102(8): 1126-1141. DOI:10.1109/jproc.2014.2320516.
[4] Delvaux J, Gu D, Schellekens D, et al. Helper data algorithms for PUF-based key generation: Overview and analysis[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(6): 889-902.
[5] Zhang J L, Lin Y P, Lyu Y Q, et al. A PUF-FSM binding scheme for FPGA IP protection and pay-per-device licensing[J]. IEEE Transactions on Information Forensics and Security, 2017, 10(6): 1137-1150.
[6] Su Y, Holleman J, Otis B. A 1.6 pJ/bit 96% stable chip-ID generating circuit using process variations [C]//IEEE International Solid-State Circuits Conference. San Francisco, CA, USA, 2007: 406-407. DOI:10.1109/isscc.2007.373466.
[7] Khan S, Hamdioui S, Kukner H, et al. Incorporating parameter variations in BTI impact on nano-scale logical gates analysis [C]//IEEE International Symposium on Defect and Fault Tolerance VLSI and Nanotechnology Systems. Austin, Texas, USA, 2012: 158-163. DOI:10.1109/dft.2012.6378217.
[8] Kastensmidt F L, Tonfat J, Both T, et al. Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs[J]. Microelectronics Reliability, 2014, 54(9): 2344-2348. DOI:10.1016/j.microrel.2014.07.100.
[9] Freijedo J F, Semião J, Rodriguez-Andina J J, et al. Modeling the effect of process, power-supply voltage and temperature variations on the timing response of nanometer digital circuits[J]. Journal of Electronic Testing, 2012, 28(4): 421-434. DOI:10.1007/s10836-012-5297-0.
[10] Stanciu A, Cirstea M N, Moldoveanu F D. Analysis and evaluation of PUF-based SoC designs for security applications[J]. IEEE Transactions on Industrial Electronics, 2016, 63(9): 5699-5708. DOI:10.1109/tie.2016.2570720.
[11] Tao S, Dubrova E. Ultra-energy-efficient temperature-stable physical unclonable function in 65 nm CMOS[J]. Electronics Letters, 2016, 52(10): 805-806. DOI:10.1049/el.2016.0292.
[12] Maiti A, Schaumont P. Improving the quality of a physical unclonable function using configurable ring oscillators [C]//International Conference on Field Programmable Logic and Applications. Prague, Czech Republic, 2009: 703-707. DOI:10.1109/fpl.2009.5272361.
[13] Cao Y, Zhang L, Chang C-H, et al. A low-power hybrid RO PUF with improved thermal stability for lightweight applications [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(7): 1143-1147.
[14] Liang H G, Xu X M, Huang Z F, et al. A methodology for characterization of SET propagation in SRAM-based FPGAs[J]. IEEE Transactions on Nuclear Science, 2016, 63(6): 2985-2992. DOI:10.1109/tns.2016.2620165.

Memo

Memo:

Biography: Liang Huaguo(1959—), male, doctor, professor, huagulg@hfut.edu.cn.
Foundation item: The National Natural Science Foundation of China(No.61674048, 61371025, 61574052, 61604001).
Citation: Liang Huaguo, Li Weidi, Xu Xiumin, et al. A method to improve PUF reliability in FPGAs[J].Journal of Southeast University(English Edition), 2018, 34(1):15-20.DOI:10.3969/j.issn.1003-7985.2018.01.003.

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