|Table of Contents|

[1] Li Zhiqun, Wang Zhigong, Zhang Liguo, Xu Yong, et al. Low phase noise LC VCO design in CMOS technology [J]. Journal of Southeast University (English Edition), 2004, 20 (1): 6-9. [doi:10.3969/j.issn.1003-7985.2004.01.002]
Copy

Low phase noise LC VCO design in CMOS technology()
CMOS工艺的低相位噪声LC VCO设计
Share：

Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
20
Issue:
2004 1
Page:
6-9
Research Field:
Circuit and System
Publishing date:
2004-03-30

Info

Title:
Low phase noise LC VCO design in CMOS technology
CMOS工艺的低相位噪声LC VCO设计
Author(s):
Li Zhiqun1;  Wang Zhigong1;  Zhang Liguo1;  Xu Yong1;  2
1Institute of RF & OE-ICs, Southeast University, Nanjing 210096, China
2 Institute of Science, PLA University of Science and Technology, Nanjing 210007, China
李智群1;  王志功1;  张立国1;  徐勇1;  2
1东南大学射频与光电集成电路研究所, 南京 210096; 2解放军理工大学理学院, 南京 210007
Keywords:
RF integrated circuit;  CMOS technology;  mixed-signal transistor;  RF transistor;  voltage controlled oscillator;  phase noise
射频集成电路;  CMOS工艺;  混合信号晶体管;  射频晶体管;  压控振荡器;  相位噪声
PACS:
TN402
DOI:
10.3969/j.issn.1003-7985.2004.01.002
Abstract:
This paper presents the design and the experimental measurements of two CMOS LC-tuned voltage controlled oscillators(VCO)implemented in a 0.18 μm 6-metal-layer mixed-signal/RF CMOS technology. The design methodologies and approaches for the optimization of the ICs are presented. The first design is optimized for mixed-signal transistor, oscillated at 2.64 GHz with a phase noise of -93.5 dBc/Hz at 500 kHz offset. The second one optimized for RF transistor, using the same architecture, oscillated at 2.61 GHz with a phase noise of -95.8 dBc/Hz at 500 kHz offset. Under a 2 V supply, the power dissipation is 8 mW, and the maximum buffered output power for mixed-signal and RF transistor are -7 dBm and -5.4 dBm, respectively. Both oscillators make use of on-chip components only, allowing for simple and robust integration.
本文介绍了用0.18 μm 6层金属混合信号/射频 CMOS工艺设计的2个 LC谐振压控振荡器及测试结果, 并给出了优化设计的方法和步骤.第1个振荡器采用混合信号晶体管设计, 振荡频率为2.64 GHz, 相位噪声为-93.5 dBc/Hz@500 kHz.第2个振荡器使用相同的电路结构, 采用射频晶体管设计, 振荡频率为2.61 GHz, 相位噪声为-95.8 dBc/Hz@500 kHz.在2 V电源下, 它们的功耗是8 mW, 最大输出功率分别为-7 dBm和-5.4 dBm. 2个振荡器均使用片上元件实现, 电路的集成简单可靠.

References:

[1] Fong Neric, Plouchart Jean-Olivier, Zamdmer Noah, et al. A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS [A]. In: Proc IEEE CICC [C]. Orlando, Florida, 2002. 423-426.
[2] Vaananen P, Metsanvirta M, Tchamov N. A 4.3 GHz VCO with 2 GHz tuning range and low phase noise [J]. IEEE J Solid-State Circuits, 2001, 36(1): 142-146.
[3] Kinget P. A fully integrated 2.7 V 0.35 μm CMOS VCO for 5 GHz wireless applications [A]. In: ISSCC Dig Tech Papers [C]. San Francisco, 1998. 226-227.
[4] Lam C, Razavi B. A 2.6 GHz/5.2 GHz CMOS VCO [A]. In: ISSCC Dig Tech Papers [C]. San Francisco, 1999. 402-403.
[5] Craninckx J, Steyaert M, Miyakawa H. A fully integrated spiral-LC CMOS VCO set with prescaler for GSM and DCS-1800 systems [A]. In: Proc IEEE CICC [C]. Santa Clara, 1997. 403-406.

Memo

Memo:
Biographies: Li Zhiqun(1959—), male, doctor, associate professor, zhiqunli@seu.edu.cn; Wang Zhigong, male, doctor, professor, zgwang@seu.edu.cn.
Last Update: 2004-03-20