[1] Ding JingfengWang ZhigongZhu EnWang GuiXia Chunxiao, Xiong Mingzhen,. 10 Gbit/s 0.25 μm CMOS 1:4 demultiplexer [J]. Journal of Southeast University (English Edition), 2005, 21 (2): 141-144. [doi:10.3969/j.issn.1003-7985.2005.02.005]

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10 Gbit/s 0.25 μm CMOS 1:4 demultiplexer()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

21

Issue:

2005 2

Page:

141-144

Research Field:

Electronic Science and Engineering

Publishing date:

2005-06-30

Info

Title:

10 Gbit/s 0.25 μm CMOS 1:4 demultiplexer

Author(s):

Ding JingfengWang ZhigongZhu EnWang GuiXia Chunxiao;  Xiong Mingzhen

Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China

Keywords:

optical receive;  complementary metal-oxide-semiconductor(CMOS);  demultiplexer(DEMUX);  latch

PACS:

TN722

DOI:

10.3969/j.issn.1003-7985.2005.02.005

Abstract:

A 10 Gbit/s(STM-64, OC-192)1:4 demultiplexer(DEMUX)with 4-phase clock was achieved in TSMC’s standard 0.25 μm complementary metal-oxide-semiconductor(CMOS)technique.All of the circuits are in source coupled FET logic(SCFL)to achieve as high as possible speed and suppress common mode distortions.This DEMUX is featured by constant-delay buffers to generate a 4-phase clock and adjust skews of the four channel outputs.The fabricated DEMUX operates error free at 10 Gbit/s by 2³¹-1 pseudorandom bit sequences(PRBS)via on-wafer testing.The measured root mean square(rms)jitter, rising and failing edge of the eye-diagram are 11, 123 and 137 ps, respectively.The chip size is 0.9 mm×1.2 mm and the power dissipation is 550 mW with a 3.3 V supply.

References:

[1] Lang M, Wang Z, Lao Z, et al.20-40 GB/s 0.2-μm GaAs HEMT chip set for optical data receiver [J].IEEE Journal of Solid-State Circuits, 1997, 32(9):1384-1393.
[2] Meghelli M, Rylyakov A V, Shan L.50 Gb/s SiGe Bi-CMOS 4 ∶1 multiplexer and 1 ∶4 demultiplexer for serial communication systems [A].In:ISSCC [C].San Francisco, 2002.260-261.
[3] Sano K, Murata K, Kitabayashi H, et al.50-GBit/s InP HEMT 4 ∶1 multiplexer/1 ∶4 demultiplexer chip set with a multiphase clock architecture [J].IEEE Trans on Microwave Theory and Technique, 2003, 51(12):2548-2554.
[4] Yen J, Case M G, Nielsen S, et al.A fully integrated 43.2 GB/s clock and data recovery and 1 ∶4 DEMUX IC in InP HBT technology [A].In:ISSCC [C].San Francisco, 2003.240-241.
[5] Tanabe A, Umetani M, Fujiwara I, et al.0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation [J].IEEE Journal of Solid-State Circuits, 2001, 36(6):988-996.
[6] Kelhrer D, Wohlmuth H, Knapp H, et al.40-Gb/s 2 ∶1 multiplexer and 1 ∶2 demultiplexer in 120 nm CMOS [A].In:ISSCC [C].San Francisco, 2003.344-349.
[7] Plouchart J, Kim J, Zamdmer N, et al.A 31GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technology [A].In:ESSCIRC [C].Lisbon, Portugal, 2003.357-360.

Memo

Memo:

Biographies: Ding Jingfeng(1976—), male, graduate;Wang Zhigong(corresponding author), male, doctor, professor, zgwang@seu.edu.cn.

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