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[1] Ma LiWang ZhigongXu Jian,. A signal-summing programmable gain amplifier employingbinary-weighted switching and constant-gm bias [J]. Journal of Southeast University (English Edition), 2017, 33 (2): 134-139. [doi:10.3969/j.issn.1003-7985.2017.02.002]
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A signal-summing programmable gain amplifier employingbinary-weighted switching and constant-gm bias()
带有二进制开关和恒跨导偏置的信号求和型可编程增益放大器
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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
33
Issue:
2017 2
Page:
134-139
Research Field:
Circuit and System
Publishing date:
2017-06-30

Info

Title:
A signal-summing programmable gain amplifier employingbinary-weighted switching and constant-gm bias
带有二进制开关和恒跨导偏置的信号求和型可编程增益放大器
Author(s):
Ma LiWang ZhigongXu Jian
Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
马力, 王志功, 徐建
东南大学射频光电与集成电路研究所, 南京 210096
Keywords:
programmable gain amplifier;  variable gain amplifier;  signal-summing topology;  constant-gm
可编程增益放大器;  可变增益放大器;  信号求和结构;  恒跨导偏置
PACS:
TN43
DOI:
10.3969/j.issn.1003-7985.2017.02.002
Abstract:
A novel programmable gain amplifier(PGA)based on a signal-summing topology is proposed. Different from conventional signal-summing variable gain amplifiers(VGA), a binary-weighted switching technique is employed to vary the current-steering transistors’ aspect ratio to change their transconductance, and hence, an accurate gain step size of 6 dB is achieved. The constant-gm biasing technique and the matching of the transistors and resistors ensures that the gain of the proposed topology is independent of the variation of process, voltage and temperature(PVT). P-well NMOS(N-metal oxide semiconductor)transistors are utilized to eliminate the influence of back-gate effect which will induce gain error. The source-degeneration technique ensures good linearity performance at a low gain. The proposed PGA is fabricated in a 0.18 μm CMOS(complementary metal oxide semiconductor)process. The measurement results show a variable gain ranging from 0 to 24 dB with a step size of 6 dB and a maximum gain error of 0.3 dB. A constant 3 dB bandwidth of 210 MHz is achieved at different gain settings. The measured output 3rd intercept point(OIP3)and minimum noise figure(NF)are 20.9 dBm and 11.1 dB, respectively. The whole PGA has a compact layout of 0.068 mm2. The total power consumption is 4.8 mW under a 1.8 V supply voltage.
提出了一种基于信号求和结构的新型可编程增益放大器.不同于传统的信号求和可变增益放大器, 在本设计中, 通过二进制开关的控制接入分流管的宽长比来实现分流管的跨导改变.二进制的设计可以实现精确的6 dB增益步长.恒跨导偏置技术保证了电路实现精确的增益, 且不受工艺、电压和温度变化的影响.P-well NMOS技术消除了背栅效应对增益误差的影响.低增益采用源极退化技术实现, 实现了信号强度较大时, 电路具有高线性度.所设计的可编程增益放大器采用0.18 μm CMOS工艺制造.测试结果显示, 增益范围为0~24 dB, 增益步长6 dB, 最大增益误差为0.3 dB.在不同增益下, 电路都能保证恒定210 MHz带宽.OIP3和最小噪声系数分别为20.9 dBm和11.1 dB.电路版图紧凑, 核心面积为0.068 mm2.在1.8 V的电源电压下, 消耗4.8 mW功率.

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Memo

Memo:
Biographies: Ma Li(1989—), male, doctor; Wang Zhigong(corresponding author), male, doctor, professor, zgwang@seu.edu.cn.
Foundation item: The National Natural Science Foundation of China(No.61306069).
Citation: Ma Li, Wang Zhigong, Xu Jian. A signal-summing programmable gain amplifier employing binary-weighted switching and constant-gm bias[J].Journal of Southeast University(English Edition), 2017, 33(2):134-139.DOI:10.3969/j.issn.1003-7985.2017.02.002.
Last Update: 2017-06-20