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[1] Zhang Baoning, Ge Wei, Wang Zhen,. A distributed cross-domain register filefor reconfigurable cryptographic processor [J]. Journal of Southeast University (English Edition), 2017, 33 (3): 260-265. [doi:10.3969/j.issn.1003-7985.2017.03.002]
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A distributed cross-domain register filefor reconfigurable cryptographic processor()
一种面向可重构密码处理器的分布式跨域寄存器文件
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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
33
Issue:
2017 3
Page:
260-265
Research Field:
Computer Science and Engineering
Publishing date:
2017-09-30

Info

Title:
A distributed cross-domain register filefor reconfigurable cryptographic processor
一种面向可重构密码处理器的分布式跨域寄存器文件
Author(s):
Zhang Baoning1 Ge Wei2 Wang Zhen2
1 School of Electronic Science and Engineering, Nanjing University, Nanjing 210023, China
2National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China
张保宁1 葛伟2 王镇2
1南京大学电子科学与工程学院, 南京 210023; 2东南大学国家专用集成电路研究中心, 南京 210096
Keywords:
reconfigurable processor block cipher parallel implementation register file
可重构处理器 分组密码 并行实现 寄存器文件
PACS:
TP302
DOI:
10.3969/j.issn.1003-7985.2017.03.002
Abstract:
Due to the fact that the register files seriously affect the performance and area of coarse-grained reconfigurable cryptographic processors, an efficient structure of the distributed cross-domain register file is proposed to realize a cryptographic processor with a high performance and a low area cost. In order to meet the demands of high performance and high flexibility at a low area cost, a union structure with the multi-ports access structure, i, e., a distributed cross-domain register file, is designed by analyzing the algorithm features of different ciphers. Considering different algorithm requirements of the global register files and local register files, the circuit design is realized by adopting different design parameters under TSMC(Taiwan Semiconductor Manufacturing Company)40 nm CMOS(complementary metal oxide semiconductor)technology and compared with other similar works. The experimental results show that the proposed distributed cross-domain register structure can effectively improve the performance of the unit area, of which the total performance of block per cycle is improved by 17.79% and performance of block per cycle per area is improved by 117%.
由于寄存器文件严重影响可重构密码处理器的性能和面积, 为了实现高性能和低面积消耗的密码处理器, 提出了一种高效的分布式跨域寄存器结构.通过分析不同分组密码的算法特点, 设计了统一的多端口访问结构——分布式跨域寄存器文件.针对全局寄存器文件和局部寄存器文件不同的算法需求, 在TSMC 40 nm CMOS工艺下, 采用不同设计参数分别完成电路实现并与类似结构做比较.实验结果显示, 所提出的分布式跨域寄存器结构能够有效地提升单位面积的性能, 其中单位时间分组密码性能提升了17.79%, 单位面积时间分组密码性能提升了117%.

References:

[1] Liu B, Baas B M. Parallel AES encryption engines for many-core processor arrays[J]. IEEE Transactions on Computers, 2013, 62(3):536-547. DOI:10.1109/tc.2011.251.
[2] Yan M, Yang Z Y, Liu L, et al. ProDFA: Accelerating domain applications with a coarse-grained runtime reconfigurable architecture[C]//IEEE 18th International Conference on Parallel and Distributed Systems (ICPADS). Singapore, 2012:834-839. DOI: 10.1109/ICPADS.2012.136.
[3] Li H, Ding J, Pan Y. Cell array reconfigurable architecture for high-efficiency AES system[J]. Microelectronics Reliability, 2012, 52(11): 2829-2836. DOI:10.1016/j.microrel.2012.04.020.
[4] Wang M Y, Su C P, Horng C L, et al. Single- and multi-core configurable AES architectures for flexible security[J]. IEEE Transactions on Very Large Scale Integration Systems, 2010, 18(4): 541-552. DOI:10.1109/tvlsi.2009.2013231.
[5] Bertoni G M, Breveglieri L, Roberto F, et al. Speeding up AES by extending a 32 bit processor instruction set[C]//International Conference on Application-Specific Systems, Architectures and Processors. Steamboat Springs, CO, USA, 2006:275-282. DOI: 10.1109/ASAP.2006.62.
[6] Mathew S K, Sheikh F, Kounavis M, et al. 53 Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45 nm high-performance microprocessors[J]. IEEE Journal of Solid-State Circuits, 2011, 46(4):767-776. DOI:10.1109/jssc.2011.2108131.
[7] Dai Z, Li W, Meng T, et al. The research and design of parallel instruction targeted at substitution box[C]//IEEE 8th International Conference on ASIC. Changsha, China, 2009: 155-158. DOI: 10.1109/ASICON.2009.5351585.
[8] Sayilar G, Chiou D. Cryptoraptor: High throughput reconfigurable cryptographic processor[C]//Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design. San Jose, CA, USA, 2014: 154-161.
[9] Shan W W, Zhang X, Fu X Y, et al. VLSI design of a reconfigurable s-box based on memory sharing method[J]. IEICE Electron Express, 2014, 11(1): 20130872. DOI:10.1587/elex.10.20130872.
[10] Singh H, Lee M H, Lu G M, et al. MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications[J]. IEEE Transactions on Computers, 2000, 49(5): 465-481. DOI:10.1109/12.859540.

Memo

Memo:
Biographies: Zhang Baoning(1978—), male, graduate; Ge Wei(corresponding author), male, doctor, assistant research fellow, duiker@seu.edu.cn.
Foundation item: The National Natural Science Foundation of China(No.61176024).
Citation: Zhang Baoning, Ge Wei, Wang Zhen.A distributed cross-domain register file for reconfigurable cryptographic processor[J].Journal of Southeast University(English Edition), 2017, 33(3):260-265.DOI:10.3969/j.issn.1003-7985.2017.03.002.
Last Update: 2017-09-20