[1] Zhou Zhigang, Cheng Shixin, Chen Ming,. Chip-level space-time equalization receiver schemefor MIMO HSDPA systems [J]. Journal of Southeast University (English Edition), 2004, 20 (2): 135-138. [doi:10.3969/j.issn.1003-7985.2004.02.001]
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Chip-level space-time equalization receiver schemefor MIMO HSDPA systems(
)
)Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]
- Volumn:
- 20
- Issue:
- 2004 2
- Page:
- 135-138
- Research Field:
- Information and Communication Engineering
- Publishing date:
- 2004-06-30
Info
- Title:
- Chip-level space-time equalization receiver schemefor MIMO HSDPA systems
- Author(s):
- Zhou Zhigang; Cheng Shixin; Chen Ming
- National Mobile Communications Research Laboratory, Southeast University, Nanjing 210096, China
- Keywords:
- multiple-input multiple-output(MIMO); chip-level; interference; minimum mean square error(MMSE); weight; space-time equalization
- PACS:
- TN929.533
- DOI:
- 10.3969/j.issn.1003-7985.2004.02.001
- Abstract:
- A chip-level space-time equalization receiver scheme is proposed for multiple-input multiple-output high-speed downlink packet access(MIMO HSDPA)systems to jointly combat the co-channel interference and the inter-code interference. A fractional sample equalizer is also derived to further improve the performance of the receiver. Performance analysis and the calculation of the output signal to interference ratio(SINR)at each receiver antenna are presented to help direct the design of equalization weight in a more optimal manner. System simulations demonstrate the significant performance gain over conventional Rake receiver and high potential of MIMO HSDPA for high-data-rate packet transmission.
References:
[1] Khirallah C, Coulton P, Zein N, et al. Performance of space-time coding for 3GPP HSDPA service under flat and frequency selective fading conditions [A]. In: Proc of Third Inter Conf on 3G Mobile Communication Technologies 2002 [C]. London, 2002. 133-136.
[2] Kwan R, Chong P H J, Poutiainen E, et al. The effect of code-multiplexing on the high speed downlink packet access(HSDPA)in a WCDMA network wireless communications and networking [A]. In: Proc of IEEE WCNC 2003 [C]. New Orleans, USA, 2003, 3: 1728 -1732.
[3] Higuchi K, Morimoto A, Abeta S, et al. Evaluation of throughput and coverage employing multipath interference canceller in high-speed downlink packet access in multipath fading channel [A]. In: Proc of IEEE 7th Inter Symp on Spread Spectrum Techniques and Applications[C]. Prague, 2002, 3: 667-671.
[4] Kawamura T, Higuchi K, Kishiyama Y, et al. Comparison between multipath interference canceller and chip equalizer in HSDPA in multipath channel [A]. In: Proc of IEEE 55th Veh Tech Conf [C]. Birmingham, 2002, 1: 459 -463.
[5] Boujemaa H, Visoz R, Berthet A. A RAKE-DFSE equalizer for the UMTS downlink [A]. In: Proc of IEEE 55th Veh Tech Conf [C]. Birmingham, 2002, 4: 1626 -1630.
[6] Ramiro-Moreno J, Pedersen K I, Mogensen P E. Network performance of transmit and receive antenna diversity in HSDPA under different packet scheduling strategies [A]. In: Proc of IEEE 57th Veh Tech Conf [C]. Orlando, 2003. 1454-1458.
[7] Davis L M, Garrett D C, Woodward G K, et al. System architecture and ASICs for a MIMO 3GPP-HSDPA receiver [A]. In: Proc of IEEE 57th Veh Tech Conf [C]. Orlando, 2003. 818-822.
[8] 3GPP, TR 25.858. High speed downlink packet access: physical layer aspects(Release 5)[EB/OL].http://www.3gpp.org/ftp/Specs/archive/25-series/25.858/25858-500.zip, 2002-03/2003-08-31.
[9] Proakis J. Digital communications. 2nd ed. [M]. McGraw-Hill Book Company, 1989.
Memo
- Memo:
- Biographies: Zhou Zhigang(1974—), male, graduate; Cheng Shixin(corresponding author), male, professor, sxcheng@seu.edu.cn.