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[1] Zhang Meng, Jia Junbo, Optimization design of 24 bit parallel MAC unit with saturation [J]. Journal of Southeast University (English Edition), 2006, 22 (4): 475-478. [doi:10.3969/j.issn.1003-7985.2006.04.007]
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Optimization design of 24 bit parallel MAC unit with saturation()
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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
22
Issue:
2006 4
Page:
475-478
Research Field:
Computer Science and Engineering
Publishing date:
2006-12-30

Info

Title:
Optimization design of 24 bit parallel MAC unit with saturation
Author(s):
Zhang Meng1;  Jia Junbo1;  2
1National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China
2 Hisilicon Technologies Co.Ltd, Shenzhen 518129, China
Keywords:
multiply-accumulate;  Booth encoding;  Wallace tree;  saturation detection;  layout design
PACS:
TP302
DOI:
10.3969/j.issn.1003-7985.2006.04.007
Abstract:
An efficient design method for a 24×24 bit+48 bit parallel saturating multiply-accumulate(MAC)unit is described.The augend in the MAC is merged as a partial product into Wallace tree array.The optimized saturation detection logic is proposed.The 679.2 μm×132.5 μm area size has been achieved in 0.18 μm 1.8 V 1P6M CMOS technology by the full-custom circuit layout design.The simulation results show that the design way has significantly less area(about 23.52% reduction)and less delay than those of the common saturating MAC based on standard cell library.

References:

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[2] Itoh Niichi, Naemura Yuka, Makino Hiroshi, et al.A 600 MHz 54×54 bit multiplier with rectangular-styled Wallace tree[J].IEEE Journal of Sold-State Circuits, 2001, 36(2):249-257.
[3] Mustafa Gok.Integer multiplier and squarer architectures with overflow detection [D].Bethlehem:EECS Department of Lehigh University, 2003.
[4] Yadav N, Schulte M J, Glossner J.Parallel saturating fractional arithmetic units[A].In:Proc of the Ninth Great Lakes Symp on VLSI[C]. Michigan, 1999. 214-217.
[5] Balzola P I, Schulte M J, Ruan, J, et al.Design alternatives for parallel saturating multioperand adders[A].In:Proc of the International Conference on Computer Design[C].Austin:VLSI in Computers & Processors, 2001.172-177.
[6] Schulte M J, Balzola P I, Akkas A, et al.Integer multiplication with overflow detection or saturation[J].IEEE Transactions on Computers, 2000, 49(7):681-691.
[7] Fadavi-Ardekani Jalil.M×N Booth encoded multiplier generator using optimized Wallace tree[J].IEEE Transactions on VLSI Systems, 1993, 1(2): 120-125.

Memo

Memo:
Biography: Zhang Meng(1964—), male, associate professor, zmeng@seu.edu.cn.
Last Update: 2006-12-20