[1] Wang Jiangang, Ruan Xinbo,. Integrated power electronics modulebased on chip scale packaged power devices [J]. Journal of Southeast University (English Edition), 2009, 25 (3): 367-371. [doi:10.3969/j.issn.1003-7985.2009.03.017]

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Integrated power electronics modulebased on chip scale packaged power devices()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

25

Issue:

2009 3

Page:

367-371

Research Field:

Electrical Engineering

Publishing date:

2009-09-30

Info

Title:

Integrated power electronics modulebased on chip scale packaged power devices

Author(s):

Wang Jiangang¹;  2;  Ruan Xinbo²

¹College of Electrical Engineering, Yancheng Institute of Technology, Yancheng 224051, China
²College of Automation Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China

Keywords:

integrated power electronics module;  chip scale package;  reliability;  parasitic parameter;  thermal management

PACS:

TM461

DOI:

10.3969/j.issn.1003-7985.2009.03.017

Abstract:

High performance can be obtained for the integrated power electronics module(IPEM)by using a three-dimensional packaging structure instead of a planar structure. A three-dimensional packaged half bridge-IPEM(HB-IPEM), consisting of two chip scale packaged MOSFETs and the corresponding gate driver and protection circuits, is fabricated at the laboratory. The reliability of the IPEM is controlled from the shape design of solder joints and the control of assembly process parameters. The parasitic parameters are extracted using Agilent 4395A impedance analyzer for building the parasitic parameter model of the HB-IPEM. A 12 V/3 A output synchronous rectifier Buck converter using the HB-IPEM is built to test the electrical performance of the HB-IPEM. Low voltage spikes on two MOSFETs illustrate that the three-dimensional package of the HB-IPEM can decrease parasitic inductance. Temperature distribution simulation results of the HB-IPEM using FLOTHERM are given. Heat dissipation of the solder joints makes the peak junction temperature of the chip drop obviously. The package realizes three-dimensional heat dissipation and has better thermal management.

References:

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[10] Fairchildsemi Corporation. Advanced packaging product [EB/OL].(2004-04-30)[2008-08-18].http: //www.fairchildsemi.com/products/discrete/adv_-pkg.html.
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Memo

Memo:

Biography: Wang Jiangang(1968—), female, doctor, associate professor, wangjg@ycit.cn.
Foundation items: Fok Ying Tung Education Foundation(No.91058), the Natural Science Foundation of High Education Institutions of Jiangsu Province(No.08KJD470004), Qing Lan Project of Jiangsu Province of 2008.
Citation: Wang Jiangang, Ruan Xinbo. Integrated power electronics module based on chip scale packaged power devices[J]. Journal of Southeast University(English Edition), 2009, 25(3): 367-371.

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