[1] Liang YongWang Zhigong, Meng QiaoGuo Xiaodan,. FPGA implementation of bit-stream neuron and perceptronbased on sigma delta modulation [J]. Journal of Southeast University (English Edition), 2012, 28 (3): 282-286. [doi:10.3969/j.issn.1003-7985.2012.03.005]

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FPGA implementation of bit-stream neuron and perceptronbased on sigma delta modulation()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

28

Issue:

2012 3

Page:

282-286

Research Field:

Electronic Science and Engineering

Publishing date:

2012-09-30

Info

Title:

FPGA implementation of bit-stream neuron and perceptronbased on sigma delta modulation

Author(s):

Liang YongWang Zhigong;  Meng QiaoGuo Xiaodan

Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China

Keywords:

bit-stream;  artificial neuron;  perceptron;  sigma delta;  field programmable gate array(FPGA)

PACS:

TN710

DOI:

10.3969/j.issn.1003-7985.2012.03.005

Abstract:

To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network(ANN)hardware implementation methods, a bit-stream ANN hardware implementation method based on sigma delta(ΣΔ)modulation is presented. The bit-stream adder, multiplier, threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array(FPGA), and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron. The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier. The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification. The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources.

References:

[1] Zhang D, Li H, Foo S Y. A simplified FPGA implementation of neural network algorithms integrated with stochastic theory for power electronics applications [C]//31st Annual Conference of the IEEE Industrial Electronics Society. Raleigh, USA, 2005: 1018-1023.
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[7] Ng C W, Wong N, Ng T S. Bit-stream adders and multipliers for tri-level sigma-delta modulators [J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2007, 54(12): 1082-1086.
[8] O’Leary P, Maloberti F.Bit stream adder for oversampling coded data [J].Electronics Letters, 1990, 26(20): 1708-1709.
[9] Liang Y, Wang Z G, Meng Q, et al. Design of high speed high SNR bit-stream adder based on ΣΔ modulation [J]. Electronic Letters, 2010, 46(11):752-753.
[10] Fujisaka H, Kurata R, Sakamoto M, et al. Bit-stream signal processing and its application to communication systems [J]. IEE Proc Circuits Devices Syst, 2002, 149(3): 159-166.

Memo

Memo:

Biographies: Liang Yong(1971—), male, doctor, associate professor; Wang Zhigong(corresponding author), male, doctor, professor, zgwang@seu.edu.cn.
Foundation items: The National Natural Science Foundation of China(No.60576028), the Natural Science Foundation of Higher Education Institutions of Jiangsu Province(No.11KJB510004).
Citation: Liang Yong, Wang Zhigong, Meng Qiao, et al.FPGA implementation of bit-stream neuron and perceptron based on sigma delta modulation[J].Journal of Southeast University(English Edition), 2012, 28(3):282-286.[doi:10.3969/j.issn.1003-7985.2012.03.005]

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