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[1] Wang Jianxin, Zhu En,. A high-throughput VLSI design for JPEG2000 9/7discrete wavelet transform [J]. Journal of Southeast University (English Edition), 2015, 31 (1): 19-24. [doi:10.3969/j.issn.1003-7985.2015.01.004]
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A high-throughput VLSI design for JPEG2000 9/7discrete wavelet transform()
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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
31
Issue:
2015 1
Page:
19-24
Research Field:
Circuit and System
Publishing date:
2015-03-30

Info

Title:
A high-throughput VLSI design for JPEG2000 9/7discrete wavelet transform
Author(s):
Wang Jianxin Zhu En
School of Information Science and Engineering, Southeast University, Nanjing 210096, China
Keywords:
JPEG2000 flipping structure 2D discrete wavelet transform(DWT) 9/7 DWT very large scale integration(VLSI)
PACS:
TN47
DOI:
10.3969/j.issn.1003-7985.2015.01.004
Abstract:
To achieve high parallel computation of discrete wavelet transform(DWT)in JPEG2000, a high-throughput two-dimensional(2D)9/7 DWT very large scale integration(VLSI)design is proposed, in which the row processor is based on flipping structure. Due to the difference of the input data flow, the column processor is obtained by adding the input selector and data buffer to the row processor. Normalization steps in row and column DWT are combined to reduce the number of multipliers, and the rationality is verified. By rearranging the output of four-line row DWT with a multiplexer(MUX), the amount of data processed by each column processor becomes half, and the four-input/four-output architecture is implemented. For an image with the size of N×N, the computing time of one-level 2D 9/7 DWT is 0.25N2+1.5N clock cycles. The critical path delay is one multiplier delay, and only 5N internal memory is required. The results of post-route simulation on FPGA show that clock frequency reaches 136 MHz, and the throughput is 544 Msample/s, which satisfies the requirements of high-speed applications.

References:

[1] Taubman D, Marcellin M. JPEG2000 image compression fundamentals, standards and practice[M]. Norwell, MA, USA: Kluwer Academic Publishers, 2001: 248.
[2] Vishwanath M, Owens R M, Irwin M J. VLSI architectures for the discrete wavelet transform [J]. IEEE Transactions on Circuits and Systems Ⅱ: Analog and Digital Signal Processing, 1995, 42(5):305-316.
[3] Chakrabarti C, Vishwanath M. Efficient realizations of the discrete and continuous wavelet transforms: from single chip implementations to mappings on SIMD array computers [J]. IEEE Transactions on Signal Processing, 1995, 43(3): 759-771.
[4] Parhi K K, Nishitani T. VLSI architectures for discrete wavelet transforms [J]. IEEE Transactions on Very Large Scale Integration Systems, 1993, 1(2): 191-202.
[5] Chakrabarti C, Vishwanath M, Owens R M. Architectures for wavelet transforms: a survey [J]. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 1996, 14(2): 171-192.
[6] Zervas N D, Anagnostopoulos G P, Spiliotopoulos V, et al. Evaluation of design alternatives for the 2-D-discrete wavelet transform [J]. IEEE Transactions on Circuits and Systems for Video Technology, 2001, 11(12): 1246-1262.
[7] Sweldens W. Lifting scheme: the new philosophy in biorthogonal wavelet constructions [C]//Wavelet Applications in Signal and Image Processing Ⅲ. San Diego, CA, USA, 1995, 2569: 68-79.
[8] Daubechies I, Sweldens W. Factoring wavelet transforms into lifting steps [J]. Journal of Fourier Analysis and Applications, 1998, 4(3): 247-269.
[9] Huang C T, Tseng P C, Chen L G. Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform [J]. IEEE Transactions on Signal Processing, 2004, 52(4): 1080-1089.
[10] Tian X, Wu L, Tan Y H, et al. Efficient multi-input/multi-output VLSI architecture for two-dimensional lifting-based discrete wavelet transform [J]. IEEE Transactions on Computers, 2011, 60(8): 1207-1211.
[11] Wu B F, Lin C F. A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec [J]. IEEE Transactions on Circuits and Systems for Video Technology, 2005, 15(12): 1615-1628.

Memo

Memo:
Biographies: Wang Jianxin(1989—), male, graduate; Zhu En(corresponding author), male, doctor, professor, zhuenpro@seu.edu.cn.
Foundation item: The National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2014ZX03003007-009).
Citation: Wang Jianxin, Zhu En. A high-throughput VLSI design for JPEG2000 9/7 discrete wavelet transform[J].Journal of Southeast University(English Edition), 2015, 31(1):19-24.[doi:10.3969/j.issn.1003-7985.2015.01.004]
Last Update: 2015-03-20