|Table of Contents|

[1] Xiao Jie, Ma Weifeng, William Lee, Shi Zhanhui, et al. A weighted averaging method for signal probabilityof logic circuit combined with reconvergent fan-out structures [J]. Journal of Southeast University (English Edition), 2018, (2): 173-181. [doi:10.3969/j.issn.1003-7985.2018.02.005]
Copy

A weighted averaging method for signal probabilityof logic circuit combined with reconvergent fan-out structures()
Share:

Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
Issue:
2018 2
Page:
173-181
Research Field:
Computer Science and Engineering
Publishing date:
2018-06-20

Info

Title:
A weighted averaging method for signal probabilityof logic circuit combined with reconvergent fan-out structures
Author(s):
Xiao Jie Ma Weifeng William Lee Shi Zhanhui
College of Computer Science and Technology, Zhejiang University of Technology, Hangzhou 310023, China
Keywords:
improved weighted averaging algorithm signal probability estimation gate error rate combinational logic circuits
PACS:
TP331
DOI:
10.3969/j.issn.1003-7985.2018.02.005
Abstract:
By analyzing the structures of circuits, a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed. Considering the failure probability of the gate, first, the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal convergence. Secondly, the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability calculation. Then, the weighted signal probability was calculated by combining the weighted average approach to correct the signal probability. Finally, the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the accuracy. Simulation results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate, and its accuracy is 4.2% higher than that of the IWAA.

References:

[1] Xiao J, Lou J G, Jiang J H, et al. Blockchain architecture reliability-based measurement for circuit unit importance [J]. IEEE Access, 2018, 6(4): 15326-15334. DOI:10.1109/access.2018.2800712.
[2] Vaghef V H, Peiravi A. A graph based approach for reliability analysis of nano-scale VLSI logic circuits[J].Microelectronics Reliability, 2014, 54(6/7):1299-1306. DOI:10.1016/j.microrel.2014.01.017.
[3] Yu C C, Hayes J P. Scalable and accurate estimation of probabilistic behavior in sequential circuits[C]// 2010 28th IEEE VLSI Test Symposium. Santa Cruz, CA, USA, 2010: 165-170. DOI:10.1109/vts.2010.5469586.
[4] Ercolani S, Favalli M, Damiani M, et al. Estimate of signal probability in combinational logic networks[C]// 1989 1st European Test Conference. Paris, France, 1989: 132-138. DOI:10.1109/etc.1989.36234.
[5] Krishnamurthy B, Tollis I G. Improved techniques for estimating signal probabilities[J].IEEE Transactions on Computers, 1989, 38(7): 1041-1045. DOI:10.1109/12.30854.
[6] Fan Y, Xiang D, Wei D Z. A new signal probability calculation method[J].Microelectronics & Computer, 1995(1): 8-10.(in Chinese)
[7] Choudhury M R, Mohanram K. Reliability analysis of logic circuits[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009, 28(3): 392-405. DOI:10.1109/tcad.2009.2012530.
[8] Han J, Chen H, Boykin E, et al. Reliability evaluation of logic circuits using probabilistic gate models[J].Microelectronics Reliability, 2011, 51(2): 468-476. DOI:10.1016/j.microrel.2010.07.154.
[9] Cai S. An efficient reliability estimation method for gate-level circuit[J].Journal of Electronics & Information Technology, 2014, 35(5): 1262-1266. DOI:10.3724/sp.j.1146.2012.01169.
[10] Zandevakili H, Mahani A, Saneei M. An accurate and fast reliability analysis method for logic circuits[J].COMPEL— The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, 2015, 34(3): 979-995.
[11] Xiao J, Lee W, Jiang J, et al. Circuit reliability estimation based on an iterative PTM model with hybrid coding[J].Microelectronics Journal, 2016, 52: 117-123. DOI:10.1016/j.mejo.2016.03.013.
[12] Rejimon T, Lingasubramanian K, Bhanja S. Probabilistic error modeling for nano-domain logic circuits[J]. IEEE Transactions on Very Large Scale Integration Systems, 2009, 17(1): 55-65. DOI:10.1109/tvlsi.2008.2003167.
[13] Abdollahi A. Probabilistic decision diagrams for exact probabilistic analysis[C]// IEEE/ACM International Conference on Computer-Aided Design. San Jose, CA, USA, 2007: 266-272.
[14] Han J, Chen H, Liang J, et al. A stochastic computational approach for accurate and efficient reliability evaluation[J].IEEE Transactions on Computers, 2014, 63(6):1336-1350. DOI:10.1109/tc.2012.276.
[15] Ibrahim W, Shousha M, Chinneck J W. Accurate and efficient estimation of logic circuits reliability bounds[J].IEEE Transactions on Computers, 2015, 64(5): 1217-1229. DOI:10.1109/tc.2014.2315633.
[16] Vaghef V H, Peiravi A. Node-to-node error sensitivity analysis using a graph based approach for VLSI logic circuits[J].Microelectronics Reliability, 2014, 55(1): 264-271. DOI:10.1016/j.microrel.2014.09.010.
[17] Taylor E, Han J, Fortes J. Towards accurate and efficient reliability modeling of nanoelectronic circuits[C]//2006 Sixth IEEE Conference on Nanotechnology(IEEE-NANO). Cincinnati, OH, USA, 2006: 395-398.
[18] Xiao J, Lee W, Jiang J H, et al. Sensitivity evaluation of input vectors with masking effects in digital circuits [J]. Chinese Journal of Computers, 2017, 40(38): 1-14.(in Chinese)

Memo

Memo:
Biography: Xiao Jie(1984—), male, doctor, lecturer, xiaojiexqj@foxmail.com.
Foundation items: The National Natural Science Foundation of China(No.61502422), the Natural Science Foundation of Zhejiang Province(No.LY18F020028, LQ15F020006), the Natural Science Foundation of Zhejiang University of Technology(No.2014XY007).
Citation: Xiao Jie, Ma Weifeng, William Lee, et al. A weighted averaging method for signal probability of logic circuit combined with reconvergent fan-out structures[J].Journal of Southeast University(English Edition), 2018, 34(2):173-181.DOI:10.3969/j.issn.1003-7985.2018.02.005.
Last Update: 2018-06-20