Fig.1 The schematic cross-section structure of the trench-gate MOSFET
Abstract：A novel simulation program with an integrated circuit emphasis (SPICE) model developed for trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET) devices is proposed. The drift region resistance was modeled according to the physical characteristics and the specific structure of the trench-gate MOSFET device. For the accurate simulation of dynamic characteristics, three important capacitances, gate-to-drain capacitanceCgd, gate-to-source capacitance Cgs and drain-to-source capacitance Cds, were modeled, respectively, in the proposed model. Furthermore, the self-heating effect, temperature effect and breakdown characteristic were taken into account; the self-heating model and breakdown model were built in the proposed model; and the temperature parameters of the model were revised. The proposed model is verified by experimental results, and the errors between measured data and simulation results of the novel model are less than 5%. Therefore, the model can give an accurate description for both the static and dynamic characteristics of the trench-gate MOSFET device.
Key words：trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET); simulation program with integrated circuit emphasis (SPICE) model; drift region resistance model; dynamic model
The trench-gate MOSFET is considered to be one of the most promising devices for power switching at voltages up to 100 V due to its low on-resistance and low gate charge[1-3]. Therefore, much attention has been focused on the development of the trench-gate MOSFET[4-5].With the wide application of the trench-gate MOSFET device, an accurate and efficient SPICE model of trench-gate MOSFET is urgently needed for the design and simulation of power circuits.
Many studies about power MOSFET modeling have been reported[6-7]. These studies mainly focus on the modeling of double diffused MOSFET (DMOSFET). Since the gate of the trench-gate MOSFET extends into the N-drift region, the parasitic JEFT region of the conventional DMOSFET is eliminated. Therefore, the conventional models of power DMOSFET cannot reflect the drift region resistance of the trench-gate MOSFET and they are also unsuitable for the trench-gate MOSFET.
In this paper, a novel SPICE model of trench-gate MOSFET is proposed. In the static modeling section, the effect of accumulation and depletion regimes upon drift region resistance was considered under different gates and drain biases to model the drift region resistance accurately.
For the dynamic characteristics of trench-gate MOSFET, three important capacitances, drain-to-source capacitance Cds, gate-to-source capacitance Cgs, and gate-to-drain capacitance Cgd, which have the significant effects on transient characteristics, were modeled, respectively. Besides, the self-heating effect and temperature effect were taken into account. In order to evaluate the reliability of the trench-gate MOSFET device, the breakdown voltage model was also included in the proposed model. According to the simulation results of the novel model and measured data, the errors of all the validations are less than 5%. Therefore, the proposed model gives a good description for trench-gate MOSFET devices.
Fig.1 shows the schematic cross-section structure of the trench-gate MOSFET. As shown in the figure, the trench gate extends into the N- epitaxial layer, and as the gate voltage is larger than the flat band voltage, the accumulation region is formed along with the trench wall within the drift region. Furthermore, for different values of gate bias, the bottom of the trench-gate edge operates in different regimes, accumulation or depletion. However, the drift region which is the closest to the drain terminal is barely influenced by the variation of gate bias. According to this feature, the drift region can be separated into two parts: region A and region B. The resistance of region A is dependent on the gate bias and drain bias, while the resistance of region B is almost completely controlled by the drain bias.
Fig.1 The schematic cross-section structure of the trench-gate MOSFET
2.1 The static model of trench-gate MOSFET
The static part of the trench-gate MOSFET model is shown in Fig.2. The properties of the MOSFET core in the trench-gate MOSFET structure are captured by using the advanced low voltage model BSIM3v3, and the influences of region A and region B for static characteristic are presented as two resistors, which are RA and RB. Besides, the breakdown voltage model is built as a sub-circuit (the diode Dbreak in series with the controlled source Ebreak).
Fig.2 The static model of trench-gate MOSFET
2.1.1 Drift region resistance model
The simulations of technology computer aided design (TCAD) reveal that, for lower Vgs, i.e. Vgs=2 V or Vgs=4 V, the current flow tends to stay away from the bottom of the trench-gate edge, and the drift region near the gate oxide operates in depletion regime[8]. For larger Vgs cases, the current flow tends to spread to the bottom of the trench-gate edge, gradually filling an otherwise depleted region, and an accumulation region is formed around the gate oxide within the drift region[9]. Therefore, the drift region can be partitioned into two sub-regions based on the current flow path. In region A, a portion of the current is confined to the accumulation layer at the trench wall, whereas in region B, the current flows throughout the total area.
According to the description above, the operating regime of region A is significantly influenced by the variation of gate and drain biases. Furthermore, due to the influence of the velocity saturation effect, the resistance of region A increases with the increase of Vds. On the other hand, as the accumulation path beside the trench wall is formed, the resistance of region A decreases with the increase of Vgs, as observed in the TCAD simulation results in Fig.3. Hence, the resistance of region A can be modeled as
(1)
where rd is the intrinsic resistance of region A; rdvd, rdvd1are the impact factors of the velocity saturation effect; and rdvg, rdvg1 are the parameters introduced by the forming accumulation path.
Fig.3 Drift region resistance of TCAD simulations
In addition, the electrical resistivity of region B depends on its carrier mobility and doping concentration. Furthermore, the carrier mobility of region B is influenced by the vertical electric field, which is dependent on Vds; therefore, the resistance of region B can be empirically modeled as
RB=rvd+rvd1Vds
(2)
where rvd is the intrinsic resistance which depends on the doping concentration of region B, and rvd1 is the parameter introduced by the carrier mobility variation caused by the vertical electric field in region B.
By synthesizing Eqs.(1) and (2), the drift region resistance Rdrift can be written as
Rdrift= RA+RB=
(3)
With the increase in temperature, the reduction of the bulk mobility in the drift region results in the increase of drift region resistance[10]. The variation of the drift region resistance can be expressed as
Rdrift(T)=Rdrift(1+TC1(T-T0)+TC2(T-T0)2)
(4)
where TC1 is the linear temperature coefficient; TC2 is the quadratic temperature coefficient for the drift region resistance; T0 is the room temperature; and T is the operating temperature.
2.1.2 Breakdown voltage model
The breakdown characteristic of the trench-gate MOSFET device is important for its reliability. When the electrical field in the impact ionization region is sufficiently large, the channel current may increase significantly and cause breakdown.
As shown in Fig.2, when the drain-to-source voltage is larger than the sum of the controlled source voltage and threshold voltage of the diode, the diode is opened-up, and then the current between drain and source becomes large. Moreover, the impact ionization is heavily influenced by temperature, and the breakdown voltage increases as the temperature increases[11]. Therefore, the characteristic of breakdown voltage Vb can be expressed as
Vb,DSS(T)= Vt,Dbreak+Ebreak(T)=
0.7+k(1+TC3(T-T0)+TC4(T-T0)2)
(5)
where TC3 is the linear temperature coefficient; TC4 is the quadratic temperature coefficient; and k is the multiplication factor.
2.2 Dynamic model of trench-gate MOSFET
As for the dynamic model of trench-gate MOSFET, we introduce three important capacitances, Cgd, Cds and Cgs. The dynamic model of the trench-gate MOSFET is completed by modeling the three capacitances accurately.
2.2.1 Model of Cds
As shown in Fig.1, Cds is mainly a depletion capacitance which is made up of the vertical Pbody-Nepi junction[12], and the drain-to-source capacitance is written as
(6)
where CJo is the zero-bias junction capacitance; pb is the junction built-in potential; mj is the varying coefficient of the junction capacitance. Therefore, as shown in Fig.4, the depletion capacitance of the body diode Dbody is used to simulate Cds.
Fig.4 Complete SPICE model of trench-gate MOSFET
2.2.2 Model of Cgd
The miller capacitance Cgd is one of the decisive factors for the dynamic characteristics of the trench-gate MOSFET[13]. As shown in Fig.1, the miller capacitance Cgd is the series combination of the gate oxide layer capacitance at the trench bottom and the depletion capacitance of the drift region. The depletion capacitance of the drift region is present only if the drain voltage is larger than the gate voltage. Moreover, the trench-gate oxide layer capacitance at the trench bottom is the parallel combination of the bottom oxide layer capacitance Cox,b and the trench sidewall oxide layer capacitance Cox,s[14]. Therefore, the Miller capacitance is presented as
(7)
Cox=Cox,b+Cox,s
(8)
(9)
where Cox is the trench bottom oxide capacitance; Cdep is the drift region depletion capacitance; Vdep is the potential difference within the drift region.
The trench gate oxide capacitance can be seen as a constant capacitance, therefore, it can be expressed as
(10)
where tox is the thickness of the gate oxide; εox is the permittivity of SiO2; W1 is the width of the oxide layer; and L1 is the length of the oxide layer.
According to the description above, the gate-to-drain capacitance can be simulated by a simple macro circuit, as shown in Fig.4, The constant capacitance C1 is used to simulate the trench bottom oxide capacitance (the capacitance C1 is much larger than the barrier capacitance of diode D1). As for the drift region depletion capacitance, it is modeled by the barrier capacitance of diode D2.
2.2.3 Model of Cgs
The capacitance Cgs consists of the channel capacitance and the overlap capacitance between gate and source. As shown in Fig.5 (extracted gate-to-source capacitance of simulation results in TCAD), with the increase of Vgs, Cgs decreases first, then it increases nearly to a constant.
Fig.5 Gate-to-source capacitance under f=1 MHz and Vd=0 V
According to the characteristic shown in Fig.5, the gate-to-source capacitance Cgs can be empirically modeled as
(11)
where C1 is the zero-bias junction capacitance; α, β are the fitting factors.
2.3 Self-heating model
The self-heating effect (SHE) represents the heating of the device due to its internal power dissipation. The increase of the internal temperature mainly affects the mobility, the threshold voltage and velocity saturation in devices[15]. Fig.6 shows the standard equivalent sub-circuit used for the self-heating representation.
Fig.6 Standard equivalent sub-circuit of self-heating effect
Clearly, the self-heating effect is related to the heat dissipation capacity of devices. The area and the width of the device have a great effect on the thermal resistance and thermal capacitance. Moreover, the thermal resistance and thermal capacitance vary dynamically with the device temperature. Therefore, the expressions of thermal resistance and capacitance are written as
RTH=(RTH0+RTHWW+RTHLL+RTHAWL)(1+θRTH(T-T0))
(12)
CTH=(CTH0+CTHWW+CTHLL+CTHAWL)(1+θCTH(T-T0))
(13)
where RTH0, CTH0 are the intrinsic thermal resistance and thermal capacitance, respectively; RTHW, RTHL, RTHA are the thermal resistance fitting factors depending on length, width and area, respectively; CTHW, CTHL, CTHA are the thermal capacitance fitting factors depending on length, width and area; W, L are the width and length of device; and θRTH, θCTH are the temperature fitting factors.
This model is validated on the measured characteristics of a 40 V trench-gate MOSFET device. The parameters of the presented model are extracted with the model building software MBP for the later verifications of the model. In order to verify the accuracy of our model under conditions which are different from those used for parameter curve fitting, the on-resistance characteristic and gate charge characteristic of the model are validated by several simple circuit simulations.
3.1 Parameters extraction
3.1.1 Static characteristics
The static characteristics fitting results in MBP are shown in Figs.7 to 9. The comparisons of measured I-Vcurves and the novel model are shown in Fig.7. It is clear that the presented model fits the measured data well. The fitting results of breakdown characteristic with different temperatures are shown in Fig.8. In Fig.9, the output characteristic curves with and without self-heating effect are fitted, respectively.
(a)
(b)
Fig.7 Typical output and transfer characteristic curves. (a) Output under T=25 ℃ with different gate-to-drain voltages; (b) Transfer under Vds=10 V with different temperatures
Fig.8 Typical breakdown characteristic curves under Vgs=0 V with different temperatures
Fig.9 Output characteristic curves with and without self-heating effect under Vgs=4 V
According to the presented curves, it is clear that the proposed model well fits the measured data in all operation regimes at the wide temperature ranges.
3.1.2 Dynamic characteristic
The fitting results of the input capacitance Ciss (Ciss=Cgs+Cgd), output capacitance Coss (Coss=Cgs+Cds) and transfer capacitance Crss (Crss=Cgd) are presented in Fig.10, and it confirms that the presented model well fits the measured C-V curves.
Fig.10 Typical input capacitance, output capacitance and transfer capacitance curves under f=1 MHz and Vgs=0 V
According to the fitting I-V and C-V curves shown in Fig.7 to Fig.10, the parameters of the drift region resistance model, breakdown model, self-heating model and dynamic model are all extracted. Tab.1 shows the extracting main parameters of the novel model for the target device based on the above figures.
Tab.1 Main parameters for the normal MOSFET
ParametersValueParametersValueVth0/V3.4K1/V1/20.36K2/10-2-2.18345U0/(cm2·(V·s)-1)0.2Ua/10-11(m·V-1)7.2425Ub/(10-19m·V-1)21.0259Uc/10-10V-1-2.452086Vsat/(105m·s-1)1.2A01.9Ags/V-10.1
3.2 Model validation
For power semiconductor devices, the optimal value, which is the product of on-resistance and gate charge, is the indicator of device performance. In order to verify the on-resistance and gate charge of the presented model, the model has been simulated in several simple simulation circuits.
3.2.1 Static verification
As for static verification, the typical drain-to-source on-resistance curves between measured data and novel model results are shown in Fig.11. Besides, the normalized breakdown voltage with different temperatures is shown in Fig.12. It is clear that the model proposed in this paper gives an accurate description for the drift region resistance and breakdown voltage.
Tab.2 Added parameters in the proposed MOSFET
ParametersValueParametersValuerd/10-3Ω2.15445 rdvd/10-41.0097rdvd1/10-62.33 rdvg0.28531rdvg10.57694 rvd/10-41.1082rvd1/Ω0.42652 T0/℃25TC1/10-36.2285 TC2/10-61.8159CJo/(10-10F·m-2)9.2 pb/V0.238mj0.7 tox/10-8m1.5C1/10-9F1.95 α20.3725β4.0143 k39.3TC3/10-31.2504 TC4/10-61.8758RTH0/(Km2·W-1)0.051 RTHW/10-31.012RTHL/10-42.784 RTHA/10-30.592CTH0/(J·K-1)0.202 CTHW/10-37.465CTHL/10-45.113 CTHA/10-37.0282θRTH/10-24.223 θCTH/10-22.174
(a)
(b)
(c)
Fig.11 On-resistance curves. (a) Under Ids=80 A with different temperatures; (b) Under T=25 ℃ different Vgs; (c) Under Vgs=10 V and Ids=80 A
Fig.12 Breakdown voltage under Vgs=0 V and Ids=10 mA
For the validation of the self-heating model, on account of the difficulty in measuring the internal temperature of the operative target device, only the simulation results of the switching circuit are shown in Figs.13(a) and (b). As shown in the figures, the self-heating effect can be observed. Moreover, the drain-to-source current decreases with a larger duty cycle and higher frequency. Hence, the presented model can reflect the heat production of device and the power dissipation between the device and environment.
(a)
(b)
Fig.13 Simulated I-V curves of presented model with self-heating model under Vds=5 V (Vgs with a high level of 4 V and a low level of 0 V). (a) With the same period but different duty cycles; (b) With the same duty cycle but different periods
3.2.2 Dynamic verification
For dynamic verification, as shown in Fig.14, the novel model gives an accurate description to the gate
Fig.14 Typical gate charge curves under Vds=20 V and Ids=80 A
charge characteristic.
According to the specific data, the errors of all the validation are less than 5%, therefore, the proposed model gives the accurate description for both the static and dynamic characteristics.
In this paper, a novel SPICE model for the trench-gate MOSFET device is presented. During the development of the static part of the proposed model, the drift region resistance is modeled according to its physical characteristics and specific structure. To account for the dynamic characteristics of devices, three important capacitances are modeled respectively. In addition, the breakdown voltage model and the self-heating model are also included in this model. In terms of the model verification with the actual measured data of the target devices, the novel model provides an accurate description of all operation regions for both the static and dynamic characteristics of the trench-gate MOSFET device.
References：
[1]Ueda D, Takagi H, Kano G. A new vertical power MOSFET structure with extremely reduced on-resistance [J]. IEEE Transactions on Electron Devices, 1985, 32(1): 2-6. DOI:10.1109/t-ed.1985.21900.
[2]Shenai K. Optimized trench MOSFET technologies for power devices [J]. IEEE Transactions on Electron Devices, 1992, 39(6): 1435-1443. DOI:10.1109/16.137324.
[3]Bulucea C, Rossen R. Trench DMOS transistor technology for high current (100 A range) switching [J]. Solid-State Electronics, 1991, 34(5): 493-507. DOI:10.1016/0038-1101(91)90153-p.
[4]Wang Y, Liu Y J, Yu C H, et al. A novel trench-gated power MOSFET with reduced gate charge [J]. IEEE Electron Device Letters, 2015, 36(2): 165-167. DOI:10.1109/led.2014.2382112.
[5]Won J, Koo J, Cho D, et al. Power trench gate MOSFET with an integrated 6-pack configuration for a 3-phase inverter [J]. Journal of the Korean Physical Society, 2015, 67(7): 1214-1221. DOI:10.3938/jkps.67.1214.
[6]Kim Y, Fossum J. Physical DMOST modeling for high voltage IC CAD [J]. IEEE Transactions Electron Devices, 1990, 37(3): 797-803. DOI:10.1109/16.47788.
[7]Kim Y, Fossum J, Williams R, et al. New physical insights and models for high voltage LDMOS IC CAD [J]. IEEE Transactions on Electron Devices, 1991, 38(7): 1641-1649. DOI:10.1109/16.85161.
[8]Iizuka T, Fukushima K, Tanaka A, et al. Modeling of trench-gate type HV-MOSFETs for circuit simulation [J]. IEICE Transactions on Electronics, 2013, 96(5): 744-751. DOI:10.1587/transele.e96.c.744.
[9]Dharmawardana K G P, Amaratunga G A J. Modeling of high current density trench gate MOSFET [J]. IEEE Transactions on Electron Devices, 2000, 47(12): 2420-2428.
[10]Wang J, Zhao T F, Li J, et al. Characterization, modeling, and application of 10-kV SiC MOSFET [J]. IEEE Transactions on Electron Devices, 2008, 55(8): 1798-1806. DOI:10.1109/ted.2008.926650.
[11]Ho C S, Liou J J, Chen F, et al. An analytical MOSFET breakdown model including self-heating effect [J]. Solid-State Electronics, 2000, 44(1): 125-131. DOI:10.1016/s0038-1101(99)00198-7.
[12]Liu S Y, Zhu R X, Jia K, et al. A novel model of the high-voltage VDMOS for the circuit simulation [J]. Solid-State Electronics, 2014, 93: 21-26. DOI:10.1016/j.sse.2013.12.006.
[13]Alatise O, Parker-Allotey N A, Jennings M, et al. Modeling the impact of the trench depth on the gate-drain capacitance in power MOSFETs [J]. IEEE Electron Device Letters, 2011, 32(9): 1269-1271. DOI:10.1109/led.2011.2159476.
[14]Hueting R J E, Hijzen E A, Heringa A, et al. Gate-drain charge analysis for switching in power trench MOSFETS [J]. IEEE Transactions on Electron Devices, 2004, 51(8): 1323-1330. DOI:10.1109/ted.2004.832096.
[15]Chauhan Y S, Anghel C, Krummenacher F, et al. Scalable general high voltage MOSFET model including quasi-saturation and self-heating effects [J]. Solid-State Electronics, 2006, 50(11/12): 1801-1813. DOI:10.1016/j.sse.2006.09.002.
摘要：针对沟槽栅纵向双扩散场效应晶体管(trench-gate MOSFET),提出了一种新型的SPICE模型.通过对沟槽栅MOSFET器件的物理特性及其内在结构分析,建立了漂移区电阻模型.为了准确模拟器件的动态特性,对栅源电容、栅漏电容及源漏电容分别建立了模型.考虑了器件的自热效应、温度效应及击穿特性,建立了自热模型和击穿电压模型,并对模型温度参数进行了修正.通过器件测试结果验证,各参数测试结果和对应模型的仿真结果误差均小于5%.因此,该模型能准确地反映器件的静态和动态特性.
关键词：沟槽栅MOSFET;SPICE模型;漂移区电阻模型;动态模型
中图分类号：TN386
Foundation items：The National Natural Science Foundation of China (No.61604038), China Postdoctoral Science Foundation (No.2015M580376), the Natural Science Foundation of Jiangsu Province (No.BK20160691), Jiangsu Postdoctoral Science Foundation (No.1501010A).
Citation：：Liu Chao, Zhang Chunwei, Liu Siyang, et al. SPICE model of trench-gate MOSFET device[J].Journal of Southeast University (English Edition),2016,32(4):408-414.
DOI：10.3969/j.issn.1003-7985.2016.04.003.
DOI：10.3969/j.issn.1003-7985.2016.04.003
Received 2016-06-23.
Biographies：Liu Chao (1993—), male, graduate; Sun Weifeng (corresponding author), male, doctor, professor, swffrog@seu.edu.cn.