[1] 2.5 Gbit/s monolithic ICs for optical fiber transmitterand receiver in 0.35 μm CMOS process [J]. Journal of Southeast University (English Edition), 2005, 21 (3): 268-271. [doi:10.3969/j.issn.1003-7985.2005.03.005]

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2.5 Gbit/s monolithic ICs for optical fiber transmitterand receiver in 0.35 μm CMOS process()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

21

Issue:

2005 3

Page:

268-271

Research Field:

Circuit and System

Publishing date:

2005-09-30

Info

Title:

2.5 Gbit/s monolithic ICs for optical fiber transmitterand receiver in 0.35 μm CMOS process

Author(s):

-

Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China

Keywords:

optical fiber communication;  monolithic;  transmitter;  receiver

PACS:

TN402;TN492

DOI:

10.3969/j.issn.1003-7985.2005.03.005

Abstract:

2.5 Gbit/s monolithic integrated circuits(ICs)for optical fiber transmitter and receiver in 0.35 μm CMOS(complementary metal-oxide-semiconductor transistor)process are presented. The transmitter, which includes a 4〓 ∶1 multiplexer and a laser diode driver(LDD), has four 622 Mbit/s random signals as its inputs and gets a 2.5 Gbit/s driving signal as its output; the receiver detects a 2.5 Gbit/s random signal and gets four 622 Mbit/s signals at the output. The main circuits include a trans-impedance amplifier(TIA), a limiting amplifier, a clock and data recovery(CDR)unit, and a 1〓 ∶4 demultiplexer(DEMUX). Test results prove the logic functions of the transmitter to be right, and the 10% to 90% rise and fall times of transmitter’s output data eye diagram are 211.1 ps and 200 ps, respectively. The sensitivity of the receiver is measured to be better than 20 mV. The root mean square jitter of the DEMUX’s output data is 15.6 ps and that of the clock after 1〓 ∶4 frequency dividing is 1.9 ps. Two chips are both applicable to 2.5 Gbit/s optical fiber communication systems.

References:

[1] Momtaz Atshin, Cao Jun, Caresosa Mario, et al. Fully-integrated SONET OC48 transceiver in standard CMOS [A]. In: Dig Tech Pap IEEE Int Solid State Circuits Conf [C]. Piscataway, NJ, USA: Institute of Electrical and Electronics Engineers Inc., 2001. 76-77.
[2] Kishine Keiji, Ishii Kiyoshi, Hirose Masaki, et al. Low-jitter, low-power 2.5-Gb/s one-chip optical receiver IC with 1 ∶8 DEMUX [A]. In: Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting [C]. Piscataway, NJ, USA: Institute of Electrical and Electronics Engineers Inc., 1999. 177-180.
[3] Sato Fumihiko, Tezuka Hiroshi, Soda Masaaki, et al. A 2.4 Gb/s receiver and a 1 ∶16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base(SSSB)bipolar transistor [J]. IEEE Journal of Solid State Circuits, 1996, 31(10): 1451-1456.
[4] Tanabe Akira, Soda Masayuki, Nakahara Yasushi, et al. A single chip 2.4 Gb/s CMOS optical receiver IC with low substrate crosstalk preamplifier [A]. In: Dig Tech Pap IEEE Int Solid State Circuits Conf [C]. Piscataway, NJ, USA: IEEE, 1998. 304-305.
[5] Wang Zhigong, Chen Xinhua, Tao Rui, et al. 2.5 Gb/s 0.35 μm CMOS ICs for optic-fiber transceiver [A]. In: ICECS [C]. Malta, 2001. 689-692.
[6] Tao Rui, Wang Zhigong, Xie Tingting, et al. A CMOS limiting amplifier for SDH STM-16 optical receiver [J]. Electronics Letters, 2001, 37(4): 236-237.
[7] Li Lianming, Huang Ting, Feng Jun, et al. 5-Gbps 0.35 μm CMOS driver for laser diode or optical modulator [A]. In: ESSCIRC [C]. Leuven, Belgium, 2004. 279-282.

Memo

Memo:

Biography: Feng Jun(1953—), female, professor, fengjun_seu@seu.edu.cn.

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