[1] Wang Huan, Wang Zhigong, Feng Jun, Xiong Mingzhen, et al. 2.488 Gbit/s clock and data recovery circuit in 0.35 μm CMOS [J]. Journal of Southeast University (English Edition), 2006, 22 (2): 143-147. [doi:10.3969/j.issn.1003-7985.2006.02.001]

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2.488 Gbit/s clock and data recovery circuit in 0.35 μm CMOS()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

22

Issue:

2006 2

Page:

143-147

Research Field:

Circuit and System

Publishing date:

2006-06-30

Info

Title:

2.488 Gbit/s clock and data recovery circuit in 0.35 μm CMOS

Author(s):

Wang Huan;  Wang Zhigong;  Feng Jun;  Xiong Mingzhen;  Zhang Li

Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China

Keywords:

clock recovery;  data recovery;  phase-locked loop(PLL);  preprocessor

PACS:

TN402;TN492

DOI:

10.3969/j.issn.1003-7985.2006.02.001

Abstract:

The design of a 2.488 Gbit/s clock and data recovery(CDR)IC for synchronous digital hierarchy(SDH)STM-16 receiver is described.Based on the injected phase-locked loop(IPLL)and D-flip flop architectures, the CDR IC was implemented in a standard 0.35 μm complementary metal-oxide-semiconductor(CMOS)technology.With 2³¹-1 pseudorandom bit sequences(PRBS)input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate(BER).The recovered clock shows a root mean square(rms)jitter of 2.8 ps and a phase noise of -110 dBc/Hz at 100 kHz offset.The capture range of the circuit is larger than 40 MHz.With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm×1 mm.

References:

[1] Walker R, Stout C, Yen C, et al.A 2.488 Gb/s Si-bipolar clock and data recovery IC with robust loss of signal detection [A].In:Dig Tech Pap IEEE Int Solid State Circuits Conf [C].Piscataway, NJ, USA:IEEE, 1997.246-247.
[2] Scheytt J Christoph, Hanke Gerhard, Langmann Ulrich.A 0.155, 0.622 and 2.488 Gb/s automatic bit rate selecting clock and data recovery IC for bit rate transparent SDH-systems [A].In:Dig Tech Pap IEEE Int Solid State Circuits Conf [C].Piscataway, NJ, USA:IEEE, 1999.348-349.
[3] Gutierrez German, Kong Shyang, Coy Bruce.2.488 Gb/s silicon bipolar clock and data recovery IC for SONET(OC-48)[A].In:IEEE Custom Integrated Circuits Conf [C].Piscataway, NJ, USA:IEEE, 1998.575-578.
[4] Pallotta Andrea, Centurelli Francesco, Trifiletti Alessandro.A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers [A].In:Proc of International Symposium on Low Power Electronics and Design [C].Piscataway, NJ, USA:IEEE, 2000.67-72.
[5] Larsson Patrik.An offset-cancelled CMOS clock recovery/demux with a half-rate linear phase detector for 2.5 Gb/s optical communication [A].In:Dig Tech Pap IEEE Int Solid State Circuits Conf [C].Piscataway, NJ, USA:IEEE, 2001.74-75.
[6] Anand Seema Butala, Razavi Behzad.A CMOS clock recovery circuit for 2.5 Gb/s NRZ data [J].IEEE Journal of Solid-State Circuits, 2001, 36(3):432-439.
[7] Yodprasit U, Ngarmnil J.Q-enhancing technique for RF CMOS active inductor [A].In:IEEE International Symposium on Circuits and Systems [C].Piscataway, NJ, USA:IEEE, 2000.589-592.

Memo

Memo:

Biographies: Wang Huan(1976—), male, graduate;Wang Zhigong(corresponding author), male, doctor, professor, zgwang@seu.edu.cn.

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