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[1] Shao Wanxin, Feng Jun, Jiang Junjie, Zhang Li, et al. 20 Gbit/s 1 ∶2 demultiplexer of low-power using 0.18 μm CMOS [J]. Journal of Southeast University (English Edition), 2007, 23 (1): 39-42. [doi:10.3969/j.issn.1003-7985.2007.01.009]
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20 Gbit/s 1 ∶2 demultiplexer of low-power using 0.18 μm CMOS()
20 Gbit/s低功耗0.18 μm CMOS 1∶2分接器
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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
23
Issue:
2007 1
Page:
39-42
Research Field:
Electronic Science and Engineering
Publishing date:
2007-03-30

Info

Title:
20 Gbit/s 1 ∶2 demultiplexer of low-power using 0.18 μm CMOS
20 Gbit/s低功耗0.18 μm CMOS 1∶2分接器
Author(s):
Shao Wanxin, Feng Jun, Jiang Junjie, Zhang Li, Li Wei
Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
邵婉新, 冯军, 蒋俊洁, 章丽, 李伟
东南大学射频与光电集成电路研究所, 南京 210096
Keywords:
demultiplexer;  dynamic-loading;  low power;  high speed
分接器;  动态负载;  低功耗;  高速度
PACS:
TN722
DOI:
10.3969/j.issn.1003-7985.2007.01.009
Abstract:
A 1〓 ∶2 demultiplexer(DEMUX)that is fabricated using 0.18 μm CMOS(complementary metal-oxide-semiconductor transistor)technology is presented.The DEMUX consists of a master-slave-slave, master-slave D flip-flops and output buffers.The D flip-flop employs a dynamic-loading structure and common-gate topology with single clock phase for the bias transistors.The dynamic-loading structure can make the circuit work faster because it decreases the charge/discharge time of the output node, and it consumes lower power because its working current is in a switch mode.In addition, the positive feedback loop, which is made up of a cross-coupled transistor pair in the latch, speeds up the circuit.Measurement results at 20 Gbit/s 223-1 pseudo random bit sequence(PRBS)via on-wafer testing show that the 1〓 ∶2 DEMUX can operate well.The power dissipation is 108 mW with the area of 475 μm×578 μm.
采用TSMC 0.18 μm CMOS 工艺实现了一个20 Gbit/s 1:2分接器, 分接器由主-从-从、主-从D触发器和数据输出缓冲组成.D触发器单元采用动态负载结构, 其偏置晶体管采用单时钟输入的共栅结构.动态负载结构的触发器工作速度更快因为它减小了输出点的冲放电时间, 而且由于工作时电流处于开关模式, 其功耗更低.另外, 触发器中采用交叉耦合的正反馈三极管对, 加快了整个电路的速度.通过在片晶圆测试, 该芯片在输入20 Gbit/s、长度为223-1的伪随机码时工作良好.功耗仅为108 mW, 芯片面积为475 μm×578 μm.

References:

[1] Runge K, Pierson R L, Zampardi P J, et al.30 Gbit/s 1 ∶4 demultiplexer IC using AlGaAs/GaAs HBTs[J]. Electronics Letters, 1997, 33(9):765-766.
[2] Shioiri S, Soda M, Hashimoto T, et al.A 10 Gb/s SiGe bipolar framer/demultiplexer for SDH systems [C]//ISSCC Dig Tech Papers.San Francisco, 1998: 202-203.
[3] Hauenschild J, Dorschky C, Seitz R, et al.A 10 Gb/s BiCMOS clock and data recovering 1 ∶4 demultiplexer in a standard plastic package with external VCO [C]//ISSCC Dig Tech Papers.San Francisco, 1996:202-203.
[4] Wong Joseph M C, Cheung Vincent S L, Luong Howard C.A 1 V 2.5 mW 5.2 GHz frequency divider in a 0.35 μm CMOS processor [J].IEEE Journal of Solid-State Circuits, 2003, 38(10):1643-1648.
[5] Xu Yang, Feng Jun.Design of 10 Gbit/s demultiplexer in 0.18 μm CMOS [J].Electronic Engineer, 2004, 33(3):5-6.(in Chinese)
[6] Ding Jingfeng, Wang Zhigong, Qiu Yinghua, et al.A low jitter 0.2 μm PHEMT 20 Gb/s 1 ∶2 demultiplexer [C]//IEEE Conference on Electron Devices and Solid-State Circuits.Hong Kong, 2005:203-206.
[7] Suzuki Toshihide, Takahashi Tsuyoshi, Makitama Kozo, et al.Under 0.5 mW 50 Gb/s full-rate 4∶1 MUX and 1∶4 DEMUX in 0.13 μm InP HEMT technology [C]//ISSCC Dig Tech Papers. San Francisco, 2004:234-235.

Memo

Memo:
Biographies: Shao Wanxin(1982—), female, graduate;Feng Jun(corresponding author), female, professor, fengjun-seu@seu.edu.cn.
Last Update: 2007-03-20