[1] Shao Wanxin, Feng Jun, Jiang Junjie, Zhang Li, et al. 20 Gbit/s 1 ∶2 demultiplexer of low-power using 0.18 μm CMOS [J]. Journal of Southeast University (English Edition), 2007, 23 (1): 39-42. [doi:10.3969/j.issn.1003-7985.2007.01.009]

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20 Gbit/s 1 ∶2 demultiplexer of low-power using 0.18 μm CMOS()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

23

Issue:

2007 1

Page:

39-42

Research Field:

Electronic Science and Engineering

Publishing date:

2007-03-30

Info

Title:

20 Gbit/s 1 ∶2 demultiplexer of low-power using 0.18 μm CMOS

Author(s):

Shao Wanxin;  Feng Jun;  Jiang Junjie;  Zhang Li;  Li Wei

Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China

Keywords:

demultiplexer;  dynamic-loading;  low power;  high speed

PACS:

TN722

DOI:

10.3969/j.issn.1003-7985.2007.01.009

Abstract:

A 1〓 ∶2 demultiplexer(DEMUX)that is fabricated using 0.18 μm CMOS(complementary metal-oxide-semiconductor transistor)technology is presented.The DEMUX consists of a master-slave-slave, master-slave D flip-flops and output buffers.The D flip-flop employs a dynamic-loading structure and common-gate topology with single clock phase for the bias transistors.The dynamic-loading structure can make the circuit work faster because it decreases the charge/discharge time of the output node, and it consumes lower power because its working current is in a switch mode.In addition, the positive feedback loop, which is made up of a cross-coupled transistor pair in the latch, speeds up the circuit.Measurement results at 20 Gbit/s 2²³-1 pseudo random bit sequence(PRBS)via on-wafer testing show that the 1〓 ∶2 DEMUX can operate well.The power dissipation is 108 mW with the area of 475 μm×578 μm.

References:

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[2] Shioiri S, Soda M, Hashimoto T, et al.A 10 Gb/s SiGe bipolar framer/demultiplexer for SDH systems [C]//ISSCC Dig Tech Papers.San Francisco, 1998: 202-203.
[3] Hauenschild J, Dorschky C, Seitz R, et al.A 10 Gb/s BiCMOS clock and data recovering 1 ∶4 demultiplexer in a standard plastic package with external VCO [C]//ISSCC Dig Tech Papers.San Francisco, 1996:202-203.
[4] Wong Joseph M C, Cheung Vincent S L, Luong Howard C.A 1 V 2.5 mW 5.2 GHz frequency divider in a 0.35 μm CMOS processor [J].IEEE Journal of Solid-State Circuits, 2003, 38(10):1643-1648.
[5] Xu Yang, Feng Jun.Design of 10 Gbit/s demultiplexer in 0.18 μm CMOS [J].Electronic Engineer, 2004, 33(3):5-6.(in Chinese)
[6] Ding Jingfeng, Wang Zhigong, Qiu Yinghua, et al.A low jitter 0.2 μm PHEMT 20 Gb/s 1 ∶2 demultiplexer [C]//IEEE Conference on Electron Devices and Solid-State Circuits.Hong Kong, 2005:203-206.
[7] Suzuki Toshihide, Takahashi Tsuyoshi, Makitama Kozo, et al.Under 0.5 mW 50 Gb/s full-rate 4∶1 MUX and 1∶4 DEMUX in 0.13 μm InP HEMT technology [C]//ISSCC Dig Tech Papers. San Francisco, 2004:234-235.

Memo

Memo:

Biographies: Shao Wanxin(1982—), female, graduate;Feng Jun(corresponding author), female, professor, fengjun_-seu@seu.edu.cn.

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