|Table of Contents|

[1] Miao Peng, Wang Zhigong,. 10 Gbit/s PRBS tester implemented in FPGA [J]. Journal of Southeast University (English Edition), 2007, 23 (4): 516-519. [doi:10.3969/j.issn.1003-7985.2007.04.008]
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10 Gbit/s PRBS tester implemented in FPGA()
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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
23
Issue:
2007 4
Page:
516-519
Research Field:
Information and Communication Engineering
Publishing date:
2007-12-30

Info

Title:
10 Gbit/s PRBS tester implemented in FPGA
Author(s):
Miao Peng;  Wang Zhigong
Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
Keywords:
bit interleaved polarity 8(BIP-8);  synchronous digital hierarchy(SDH);  framer;  field programmable gate array(FPGA);  pseudo-random binary sequence(PRBS)
PACS:
TN913.7
DOI:
10.3969/j.issn.1003-7985.2007.04.008
Abstract:
The design of an FPGA(field programmable gate array)based programmable SONET(synchronous optical network)OC-192 10 Gbit/s PRBS(pseudo-random binary sequence)generator and a bit interleaved polarity 8(BIP-8)error detector is presented.Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 27-1, 210-1, 215-1, 223-1and 231-1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4(OC-192 serdes-framer interface).In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly.The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.

References:

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[4] Intel Corp.TXN13300/01/03 data sheet [EB/OL].(2003-03)[2006-12-15].http://www.intel.com/design/network/products/op-tical/ent-transceivers.htm.
[5] OIF Physical and Link Layer Working Group.SFI-4(OC-192 serdes-framer interface)OIF-PLL-02.0—proposal for a common electrical interface between SONET frame and serializer/deserializer parts for OC-192 interfaces):implementation agreement OIF-SFI4-01.0[EB/OL].(2000-06)[2006-12-10].http://www.oiforum.org.
[6] Xiao Guozhen.PRBS and its application[M].Beijing:National Defence Industry Press, 1985:97-98.(in Chinese)
[7] Obaidata M S, Tengb J.A methodology to analyze the performance of a parallel frame synchronization scheme in SDH high speed networks [J].Computer Communications, 1999, 9(22):644-650.
[8] Kong Dennis T.2.488 Gb/s SONET multiplexer/demultiplexer with frame detection capability [J].IEEE Journal on Selected Areas in Communications, 1991, 6(9):726-731.
[9] Li Yu, Wang Zhigong, Miao Peng.Parallel frame alignment circuit in very short reach system: CN200410014719.7 [P].2005-01-12.(in Chinese)
[10] OIF Physical and Link Layer Working Group.Very short reach(VSR)OC-192/STM-64 inter-face based on parallel optics:implementation agreement OIF-VSR4-01.0[EB/OL].(2000-06)[2006-12].http://www.oiforum.com/public/documents.
[11] Xilinx Corp.RocketIO X bit-error rate tester reference design [EB/OL].(2001-01)[2006-12-30].http://www.xilinx.com/.

Memo

Memo:
Biography: Miao Peng(1972—), male, doctor, lecturer, miaopeng123@hotmail.com.
Last Update: 2007-12-20