[1] Hu Qingsheng, Zhong Jianfeng, He Xiaohu,. 0.18 μm CMOS programmable frequency divider design for DVB-T [J]. Journal of Southeast University (English Edition), 2008, 24 (2): 159-162. [doi:10.3969/j.issn.1003-7985.2008.02.007]

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0.18 μm CMOS programmable frequency divider design for DVB-T()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

24

Issue:

2008 2

Page:

159-162

Research Field:

Circuit and System

Publishing date:

2008-06-03

Info

Title:

0.18 μm CMOS programmable frequency divider design for DVB-T

Author(s):

Hu Qingsheng;  Zhong Jianfeng;  He Xiaohu

Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China

Keywords:

programmable frequency divider;  frequency synthesizer;  standard cell;  DVB-T

PACS:

TN453

DOI:

10.3969/j.issn.1003-7985.2008.02.007

Abstract:

The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop(PLL)frequency synthesizer for digital video broadcasting-terrestrial(DVB-T)and other modern communication systems, is presented.By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387.Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology.By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model.This divider has been fabricated in TSMC 0.18 μm CMOS technology using Artisan standard cell library.The chip area is 675 μm×475 μm and the power consumption is about 2 mW under a 1.8 V power supply.Measurement results show that it works correctly and can realize a frequency division with high precision.

References:

[1] Rana R S.Dual-modulus 127/128 FOM enhanced prescaler design in 0.35 μm CMOS technology [J].IEEE Journal of Solid-State Circuits, 2005, 40(8):1662-1670.
[2] Hung C M, Kenneth K O.A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop [J].IEEE Journal of Solid-State Circuits, 2002, 37(4):521-525.
[3] Lee Thomas H, Samavati Hirad, Rategh H R.5-GHz CMOS wireless LANs [J].IEEE Transactions on Microwave Theory and Techniques, 2002, 50(1):268-279.
[4] Hung C M, Floyd B A, Kenneth K O.A fully integrated 5.35-GHz CMOS VCO and a prescaler [C]//Dig Papers 2000 IEEE RFIC Symp.Boston, MA, 2002:69-72.
[5] Yang C Y, Dehng G K, Liu S I.High-speed divide-by-4/5 counter for a dual modulus prescaler [J].Electronics Letters, 1997, 30(20):1691-1692.
[6] Chang B, Park J, Kim W.A 1.2 GHz CMOS dual modulus prescaler using new dynamic D-type flip-flops [J].IEEE Journal of Solid-State Circuits, 1996, 31(5):749-752.
[7] Yu X P, Do M A, Jia L, et al.Design of a low power wide-band high resolution programmable frequency divider [J].IEEE Transactions on VLSI Systems, 2005, 13(9):1098-1103.
[8] Tournier É, Sié M, Graffenil J.High-speed dual-modulus prescaler architecture for programmable digital frequency dividers [J].IEE Electronics Letters, 2001, 37(24):1433-1434.
[9] He Xiaohu, Hu Qingsheng, Xiao Jie.An example of back-end design for ASIC in deep submicron technology [J].China Integrated Circuit, 2006, 15(8):37-42.(in Chinese)

Memo

Memo:

Biography: Hu Qingsheng(1964—), female, doctor, professor, qshu@seu.edu.cn.
Foundation item: The National Natural Science Foundation of China(No.60472057).
Citation: Hu Qingsheng, Zhong Jianfeng, He Xiaohu.0.18 μm CMOS programmable frequency divider design for DVB-T[J].Journal of Southeast University(English Edition), 2008, 24(2):159-162.

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