[1] Hu Qingsheng, Zhong Jianfeng, He Xiaohu,. 0.18 μm CMOS programmable frequency divider design for DVB-T [J]. Journal of Southeast University (English Edition), 2008, 24 (2): 159-162. [doi:10.3969/j.issn.1003-7985.2008.02.007]
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0.18 μm CMOS programmable frequency divider design for DVB-T(
)
应用于DVB-T的0.18 μm CMOS可编程分频器设计
)Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]
- Volumn:
- 24
- Issue:
- 2008 2
- Page:
- 159-162
- Research Field:
- Circuit and System
- Publishing date:
- 2008-06-03
Info
- Title:
- 0.18 μm CMOS programmable frequency divider design for DVB-T
- 应用于DVB-T的0.18 μm CMOS可编程分频器设计
- Author(s):
- Hu Qingsheng, Zhong Jianfeng, He Xiaohu
- Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
- PACS:
- TN453
- DOI:
- 10.3969/j.issn.1003-7985.2008.02.007
- Abstract:
- The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop(PLL)frequency synthesizer for digital video broadcasting-terrestrial(DVB-T)and other modern communication systems, is presented.By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387.Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology.By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model.This divider has been fabricated in TSMC 0.18 μm CMOS technology using Artisan standard cell library.The chip area is 675 μm×475 μm and the power consumption is about 2 mW under a 1.8 V power supply.Measurement results show that it works correctly and can realize a frequency division with high precision.
- 可编程分频器是PLL频率综合器中的重要单元, 用标准单元方法实现了一种适用于数字电视地面广播(DVB-T)接收机的PLL频率综合器的可编程分频器.结合双模分频器, 所设计的分频器可实现926~1 387之间的整数分频.除了传统的逻辑综合、版图规划、布局布线等标准单元设计流程, 所设计流程中还考虑了前端设计和后端设计之间的信息交互.通过将后端信息返标到前端设计工具, 生成了用户定义的线负载模型, 该模型比缺省的模型更接近实际情况.该可编程分频器采用ARTISAN TSMC 0.18 μm CMOS标准单元库设计并流片, 芯片面积为675 μm×475 μm, 1.8 V电压下的功耗为2 mW.测试结果表明芯片工作正确, 能够完成精确的分频比.
References:
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Memo
- Memo:
-
Biography: Hu Qingsheng(1964—), female, doctor, professor, qshu@seu.edu.cn.
Foundation item: The National Natural Science Foundation of China(No.60472057).
Citation: Hu Qingsheng, Zhong Jianfeng, He Xiaohu.0.18 μm CMOS programmable frequency divider design for DVB-T[J].Journal of Southeast University(English Edition), 2008, 24(2):159-162.