[1] Wu Xiushan, Wang Zhigong, Li Zhiqun, et al. Implementation and noise optimizationof a 433 MHz low power CMOS LNA [J]. Journal of Southeast University (English Edition), 2009, 25 (1): 9-12. [doi:10.3969/j.issn.1003-7985.2009.01.003]

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Implementation and noise optimizationof a 433 MHz low power CMOS LNA()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

25

Issue:

2009 1

Page:

9-12

Research Field:

Information and Communication Engineering

Publishing date:

2009-03-30

Info

Title:

Implementation and noise optimizationof a 433 MHz low power CMOS LNA

Author(s):

Wu Xiushan¹;  2;  Wang Zhigong¹;  Li Zhiqun¹;  Li Qing²

¹ Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
² College of Electrical and Mechanical Engineering, China Jiliang University, Hangzhou 310018, China

Keywords:

low noise amplifier(LNA);  cascode;  low power;  noise figure;  noise optimization

PACS:

TN924

DOI:

10.3969/j.issn.1003-7985.2009.01.003

Abstract:

A low power 433 MHz CMOS(complementary metal-oxide-semiconductor transistor)low noise amplifier(LNA), used for an ISM(industrial-scientific-medical)receiver, is implemented in a 0.18 μm SMIC mixed-signal and RF(radio frequency)CMOS process.The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA.The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB.The S₂₁ is equal to 16 dB, S₁₁=-11 dB, S₂₂=-9 dB, and the inverse isolation is 35 dB.The measured input 1-dB compression point(P_1dB)and input third-order intermodulation product(IIP3)are -13 dBm and -3 dBm, respectively.The chip area is 0.55 mm×1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.

References:

[1] Belostotski L, Haslett J W.Noise figure optimization of inductively degenerated CMOS LNAs with integrated gate inductors[J].IEEE Transactions on Circuits and Systems Ⅰ: Regular Papers, 2006, 53(7):1409-1422.
[2] Mou Shouxian, Ma Jianguo, Yeo Kiat Seng, et al.A modified architecture used for input matching in CMOS low-noise amplifiers[J].IEEE Transactions on Circuits and Systems Ⅱ:Express Briefs, 2005, 52(11):784-788.
[3] Aly Ismail, Asad A Abidi.A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network[J].IEEE Journal of Solid-State Circuits, 2004, 39(12):2269-2277.
[4] Nguyen Trung-Kien, Kim Chung-Hwan, Ihm Gook-Ju, et al.CMOS low-noise amplifier design optimization techniques[J].IEEE Transactions on Microwave Theory and Techniques, 2004, 52(5):1433-1442.
[5] Lee Sung-Huang, Hang Eng-Zong, Chiu Chin-Fong, et al.A novel noise design method for CMOS L-degeneration cascoded LNA[C]//Proceedings of 2004 IEEE Asia-Pacific Circuits and Systems Conference.Tainan, China, 2004:273-276.
[6] Lee Jeonghoon, Kim Youngsik.A 1.8V fully differential CMOS low noise amplifier with a special care for mixer input stage[C]//The 6th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. San Diego, California, USA, 2006:178-181.
[7] van der Ziel A.Noise in solid state devices and circuits [M].New York:Wiley, Inc, 1986.
[8] Fan Xiaohua, Zhang Heng, Sánchez-Sinencio Edgar.A noise reduction and linearity improvement technique for a differential cascode LNA[J].IEEE Journal of Solid-State Circuits, 2008, 43(3):588-599.
[9] Kim Chang-Wan, Kang Min-Suk, Anh Phan Tuan, et al.An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system[J].IEEE Journal of Solid-State Circuits, 2005, 40(2):544-547.
[10] Goo Jung-Suk, Ahn Hee-Tae, Ladwig Donald J, et al.A noise optimization technique for integrated low-noise amplifier[J].IEEE Journal of Solid-State Circuits, 2002, 37(8):994-1001.

Memo

Memo:

Biographies: Wu Xiushan(1974—), male, lecturer;Wang Zhigong(corresponding author), male, doctor, professor, zgwang@seu.edu.cn.
Foundation items: The National Natural Science Foundation of China(No.60772008), the Key Science and Technology Program of Zhejiang Province(No.G2006C13024).
Citation: Wu Xiushan, Wang Zhigong, Li Zhiqun, et al.Implementation and noise optimization of a 433 MHz low power CMOS LNA[J].Journal of Southeast University(English Edition), 2009, 25(1):9-12.

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