[1] Zhang Changchun, Wang Zhigong, Shi Si, Pan Haixian, et al. A 5-Gbit/s monolithically-integrated low-power clockrecovery circuit in 0.18-μm CMOS [J]. Journal of Southeast University (English Edition), 2011, 27 (2): 136-139. [doi:10.3969/j.issn.1003-7985.2011.02.004]

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A 5-Gbit/s monolithically-integrated low-power clockrecovery circuit in 0.18-μm CMOS()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

27

Issue:

2011 2

Page:

136-139

Research Field:

Economy and Management

Publishing date:

2011-06-30

Info

Title:

A 5-Gbit/s monolithically-integrated low-power clockrecovery circuit in 0.18-μm CMOS

Author(s):

Zhang Changchun¹;  Wang Zhigong¹;  Shi Si¹;  Pan Haixian²;  Guo Yufeng¹;  Huang Jiwei¹

¹Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
²State Key Laboratory of Bioelectronics, Southeast University, Nanjing 210096, China

Keywords:

clock recovery;  phase frequency detector;  voltage-controlled oscillator;  phase noise

PACS:

N913.7

DOI:

10.3969/j.issn.1003-7985.2011.02.004

Abstract:

In order to make a 10 Gbit/s 2∶1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery(CR)circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator(VCO)is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector(PFD)is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature(PVT)variation. SMIC 0.18-μm CMOS technology is adopted and the core area is 170 μm×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of -114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.

References:

[1] Wang Huan, Wang Zhigong, Feng Jun, et al. 2.488 Gbit/s clock and data recovery circuit in 0.35 μm CMOS [J]. Journal of Southeast University: English Edition, 2006, 22(2): 143-147.
[2] Gutierrez G, Shyang K. Unaided 2.5 Gb/s silicon bipolar clock and data recovery IC [C]//IEEE Radio Frequency Integrated Circuits Symposium. Piscataway, NJ, USA: IEEE, 1998: 173-176.
[3] Gutierrez G, Shyang K, Bruce C. 2.488 Gb/s silicon bipolar clock and data recovery IC for SONET(OC-48)[C]//IEEE Custom Integrated Circuits Conference. Piscataway, NJ, USA: IEEE, 1998: 575-578.
[4] Raja M K, Yan D L, Ajjikuttira A B, et al. A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS [C]//European Solid-State Circuits Conference. Piscataway, NJ, USA: IEEE, 2007: 524-527.
[5] Chen Yingmei, Wang Zhigong, Xiong Mingzhen, et al. 2.5 Gb/s monolithic IC of clock recovery, data decision, and 1∶4 demultiplexer [J]. Chinese Journal of Semiconductors, 2005, 26(8): 1532-1536.
[6] Liu Yongwang, Wang Zhigong, Li Wei. 2.5 Gb/s 0.18 μm CMOS clock and data recovery circuit [J]. Chinese Journal of Semiconductors, 2007, 28(4): 537-541.
[7] Pottbäcker A, Langmann U, Schreiber H U. A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s [J]. IEEE Journal of Solid-State Circuits, 1992, 27(12):1747-1751.
[8] Rogers J E, Long J R. A 10 Gb/s CDR/DEMUX with LC delay line VCO in 0.18 μm CMOS [J]. IEEE Journal of Solid-State Circuits, 2002, 37(12):1781-1789.
[9] Walker R C. Designing bang-bang PLLs for clock and data recovery in serial data transmission systems [C]//Phase-Locking in High Performance Systems: From Devices to Architectures. Wiley-IEEE Press, 2003: 34-45.
[10] Razavi B. Design of integrated circuits for optical communications [M]. New York: McGraw-Hill, 2003:197-200.

Memo

Memo:

Biographies: Zhang Changchun(1981—), male, doctor; Wang Zhigong(corresponding author), male, doctor, professor, zgwang@seu.edu.cn.
Foundation items: The National High Technology Research and Development Program of China(863 Program)(No.2007AA01Z2a5), the National Natural Science Foundation of China(No.60806027, 61076073), Specialized Research Fund for the Doctoral Program of Higher Education(No.20090092120012).
Citation: Zhang Changchun, Wang Zhigong, Shi Si, et al.A 5-Gbit/s monolithically-integrated low-power clock recovery circuit in 0.18-μm CMOS[J].Journal of Southeast University(English Edition), 2011, 27(2):136-139.[doi:10.3969/j.issn.1003-7985.2011.02.004]

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