[1] Fan Chen, Wang Rong, Wang Zhigong,. Design of a 12-Gbit/s CMOS DNFFCGdifferential transimpedance amplifier [J]. Journal of Southeast University (English Edition), 2018, 34 (1): 1-5. [doi:10.3969/j.issn.1003-7985.2018.01.001]
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Design of a 12-Gbit/s CMOS DNFFCGdifferential transimpedance amplifier(
)
12 Gbit/s CMOS DNFFCG差分跨阻放大器的设计
)Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]
- Volumn:
- 34
- Issue:
- 2018 1
- Page:
- 1-5
- Research Field:
- Information and Communication Engineering
- Publishing date:
- 2018-03-20
Info
- Title:
- Design of a 12-Gbit/s CMOS DNFFCGdifferential transimpedance amplifier
- 12 Gbit/s CMOS DNFFCG差分跨阻放大器的设计
- Author(s):
- Fan Chen; Wang Rong; Wang Zhigong
- Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
- Keywords:
- very-short-reach; optoelectronic integrated circuit; negative feedback; feed-forward common gate; trans-impedance gain
- PACS:
- TN915
- DOI:
- 10.3969/j.issn.1003-7985.2018.01.001
- Abstract:
- A 12-Gbit/s low-power, wide-bandwidth CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the very-short-reach(VSR)optoelectronic integrated circuit(OEIC)receiver. The dominant pole of the input node is shifted up to a high frequency, and thus the bandwidth of the CMOS DNFFCG TIA is improved. Besides, two negative feedback loops are used to reduce the input impedance and further increase the bandwidth. The proposed TIA was fabricated using TSMC 0.18 μm CMOS technology. The whole circuit has a compact chip area, the core area of which is only 0.003 6 mm2. The power consumption is 14.6 mW excluding 2-stage differential buffers. The test results indicate that the 3 dB bandwidth of 9 GHz is achieved with a 1.8 V supply voltage and its trans-impedance gain is 49.2 dBΩ. The measured average equivalent input noise current density is 28.1 pA/Hz1/2. Under the same process conditions, the DNFFCG has better gain bandwidth product compared with those in the published papers.
- 提出了一种12-Gbit/s的低功耗、宽带CMOS具有双反馈结构的前馈共栅差分跨阻放大器, 用于甚短距离传输光电集成电路接收机.通过将输入节点的主极点提高到一个较高的频率, 增大了放大器带宽.此外, 采用2个反馈环路降低输入等效电阻, 从而进一步提高了带宽.提出的跨阻放大器采用TSMC 0.18 μm CMOS工艺制造.整个电路具有较小的芯片面积, 其核心面积仅为0.003 6 mm2.在不考虑两级差分的缓冲放大器时, 其功耗为14.6 mW.测试结果表明, 在1.8 V的电源电压下, 实现了9 GHz的3 dB带宽和49.2 dBΩ的跨阻增益.测量的平均输入噪声电流功率谱密度为28.1 pA/Hz1/2.在相同的工艺条件下, 与已发表的文献相比, DNFFCG差分跨组放大器具有最佳的增益带宽积.
References:
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Memo
- Memo:
-
Biographies: Fan Chen(1988—), male, Ph.D. candidate; Wang Rong(corresponding author), female, doctor, associate professor, wangrong@seu.edu.cn.
Foundation item: The National Natural Science Foundation of China(No.61306069).
Citation: Fan Chen, Wang Rong, Wang Zhigong. Design of a 12-Gbit/s CMOS DNFFCG differential transimpedance amplifier[J].Journal of Southeast University(English Edition), 2018, 34(1):1-5.DOI:10.3969/j.issn.1003-7985.2018.01.001.