|Table of Contents|

[1] Ni Tianming, Liang Huaguo, Nie Mu, et al. An optimal stacking order for mid-bond testing cost reductionof 3D IC [J]. Journal of Southeast University (English Edition), 2018, 34 (2): 166-172. [doi:10.3969/j.issn.1003-7985.2018.02.004]
Copy

An optimal stacking order for mid-bond testing cost reductionof 3D IC()
三维集成电路绑定中测试成本缩减的优化堆叠顺序
Share：

Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
34
Issue:
2018 2
Page:
166-172
Research Field:
Computer Science and Engineering
Publishing date:
2018-06-20

Info

Title:
An optimal stacking order for mid-bond testing cost reductionof 3D IC
三维集成电路绑定中测试成本缩减的优化堆叠顺序
Author(s):
Ni Tianming1;  2;  Liang Huaguo1;  Nie Mu3;  Bian Jingchang1 Huang Zhengfeng1;  Xu Xiumin1;  Fang Xiangsheng3
1 School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230009, China
2Department of Electronic Information and Electrical Engineering, Hefei University, Hefei 230601, China
3School of Computer and Information, Hefei University of Technology, Hefei 230009, China
倪天明1;  2;  梁华国1;  聂牧3;  卞景昌1;  黄正峰1;  徐秀敏1;  方祥圣3
1合肥工业大学电子科学与应用物理学院, 合肥230009; 2合肥学院电子信息与电气工程系, 合肥230601; 3合肥工业大学计算机与信息学院, 合肥230009
Keywords:
three-dimensional integrated circuit(3D IC);  mid-bond test cost;  stacking order;  sequential stacking;  failed bonding
三维集成电路;  绑定中测试成本;  堆叠顺序;  顺序堆叠;  绑定失效
PACS:
TP306
DOI:
10.3969/j.issn.1003-7985.2018.02.004
Abstract:
In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high, an optimal stacking order scheme is proposed to reduce the mid-bond test cost. A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors. An algorithm for testing cost and testing order optimization is proposed, and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints. To prove the influence of the optimal stacking order on testing costs, two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared. Based on the benchmarks from ITC’02, experimental results show that for a 5-layer 3D IC, under different constraints, the optimal stacking order can reduce the test costs on average by 13% and 62%, respectively, compared to the pyramid type and inverted pyramid type. Furthermore, with the increase of the stack size, the test costs of the optimized stack order can be decreased.
针对三维集成电路顺序堆叠测试成本高的问题, 提出了一种用于绑定中测试成本降低的堆叠顺序优化方案.建立了新的测试成本模型, 综合考虑了用于自动测试装备的测试时间和制造失效因素.提出了一种测试成本堆叠顺序和测试时间优化算法, 通过约束测试带宽、测试功耗等条件, 得到最小的测试成本和对应的最优堆叠次序.为了证明优化堆叠顺序对测试成本的影响, 以金字塔型和倒金字塔型2种顺序堆叠作为比较基准并进行了比较.基于ITC’02电路, 实验结果表明, 对于5层的三维集成电路, 在不同的约束条件下, 优化的堆叠顺序测试成本相比于金字塔顺序堆叠平均可以减少13%, 相对于倒金字塔顺序堆叠平均减少62%.此外, 随着堆叠数目的增加, 优化的堆栈顺序可节省更多的测试成本.

References:

[1] Agrawal M, Chakrabarty K. Test-cost modeling and optimal test-flow selection of 3D-stacked ICs [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(9):1523-1536.
[2] Agrawal M, Chakrabarty K. Test-cost optimization and test-flow selection for 3D-stacked ICs [C]//2013 IEEE 31st VLSI Test Symposium (VTS). Berkeley, CA, USA, 2013:1-6. DOI:10.1109/vts.2013.6548941.
[3] Taouil M, Hamdioui S. Test impact on the overall die-to-wafer 3D stacked IC cost [J]. Journal of Electronic Testing, 2012, 28(1):15-25.
[4] Taouil M, Hamdioui S. Stacking order impact on overall 3D die-to-wafer stacked-IC cost [C]// IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Cottbus, Germany, 2011:335-340.
[5] Liang H G, Chang H. Optimized mid-bond order for 3D stacked ICs considering failed bonding [J]. Chinese Journal of Electronics, 2015, 24(2):223-228. DOI:10.1049/cje.2015.04.001. (in Chinese)
[6] Koren I, Koren Z. Defect tolerance in VLSI circuits: Techniques and yield analysis [J]. Proceedings of the IEEE, 1998, 86(9):1819-1838. DOI:10.1109/5.705525.
[7] Chen Y, Niu D, Xie Y.Cost-effective integration of three-dimensional ICs emphasizing testing cost analysis [C]// IEEE International Conference on Computer-Aided Design. San Jose, CA, USA, 2010: 471-476.
[8] Deng Y D, Maly W P. 2.5-dimensional VLSI system integration [J]. IEEE Transactions on Very Large Scale Integration Systems, 2005, 13(6):668–677.
[9] Krishnendu C. ITC’02 SOC test benchmarks [EB/OL].(2008-08-22)[2017-05-20]. http://itc02socbenchm.pratt.duke.edu.
[10] Hsu C Y, Kuo C Y, et al. 3D IC test scheduling using simulated annealing [C]// International Symposium on VLSI Design, Automation, and Test. Hsinchu, China, 2012:1-4.
[11] Jiang L, Xu Q. Yield and reliability enhancement for 3D ICs: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist [C]// IEEE International Test Conference. Anaheim, CA, USA, 2015:1-11. DOI:10.1109/test.2015.7342423.
[12] Cadix L. Lifting the veil on silicon interposer pricing [EB/OL].(2012-12)[2017-05-20]. http://electroiq.com/blog/articles/2012/12/lifting-the-veil-on-silicon-interposer-pricing/.
[13] Wang R, Chakrabarty K, Bhawmik S. Interconnect testing and test-path scheduling for interposer-based 2.5-D ICs [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(1):136-149.DOI: 10.1109/TCAD.2014.2365097.

Memo

Memo:
Biographies: Ni Tianming( 1991— ), male, Ph.D. candidate; Liang Huaguo(corresponding author), male, professor, huagulg@hfut.edu.cn.
Foundation items: The National Natural Science Foundation of China( No.61674048, 61574052, 61474036, 61371025), the Project of Anhui Institute of Economics and Management(No.YJKT1417T01).
Citation: Ni Tianming, Liang Huaguo, Nie Mu, et al.An optimal stacking order for mid-bond testing cost reduction of 3D IC[J].Journal of Southeast University(English Edition), 2018, 34(2):166-172.DOI:10.3969/j.issn.1003-7985.2018.02.004.
Last Update: 2018-06-20