[1] Jiang Junjie, Feng Jun, Li Youhui, Hu Qingsheng, et al. A kind of low-power 10 Gbit/s CMOS 1∶4 demultiplexer [J]. Journal of Southeast University (English Edition), 2006, 22 (1): 1-4. [doi:10.3969/j.issn.1003-7985.2006.01.001]

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A kind of low-power 10 Gbit/s CMOS 1∶4 demultiplexer()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

22

Issue:

2006 1

Page:

1-4

Research Field:

Electronic Science and Engineering

Publishing date:

2006-03-20

Info

Title:

A kind of low-power 10 Gbit/s CMOS 1∶4 demultiplexer

Author(s):

Jiang Junjie;  Feng Jun;  Li Youhui;  Hu Qingsheng;  Xiong Mingzhen

Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China

Keywords:

optical communication;  CMOS;  demultiplexer(DEMUX);  low-power

PACS:

TN722

DOI:

10.3969/j.issn.1003-7985.2006.01.001

Abstract:

A 10 Gbit/s 1∶4 demultiplexer(DEMUX)fabricated in 0.18 μm CMOS(complementary metal-oxide-semiconductor transistor)technology for optical-fiber-link is presented.The system is constructed in tree-type structure and it includes a high-speed 1〓 ∶2 DEMUX, two low-speed 1〓 ∶2 DEMUXs, a divider, and input and output buffers for data and clock.To improve the circuit performance and reduce the power consumption, a latch structure with a common-gate topology and a single clock phase is employed in the high-speed 1∶2 DEMUX and the 5 GHz 1∶2 on-chip frequency divider, while dynamic CMOS logic is adopted in the low-speed 1∶2 DEMUXs.Measured results at 10 Gbit/s by 2³¹-1 pseudo random bit sequences(PRBS)via on-wafer testing indicate that it can work well with a power dissipation of less than 100 mW at 1.8 V supply voltage.The die area of the DEMUX is 0.65 mm×0.75 mm.

References:

[1] Tanabe Akira, Umetani Masato, Fujiwara Ikuo, et al.0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation [J].IEEE Journal of Solid-State Circuits, 2001, 36(6):988-996.
[2] Tanabe Akira, Nakahara Yasushi, Furukawa Akio, et al.A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC [J].IEEE Journal of Solid-State Circuits, 2003, 38(1):107-113.
[3] Runge K, Pierson R L, Zampardi P J, et al.30 Gbit/s 1∶4 demultiplexer IC using AlGaAs/GaAs HBTs [J].Electronics Letters, 1997, 33(9):765-766.
[4] Mattia John Paul, Pullela Raja, Baeyens Yves, et al.A 1∶4 demultiplexer for 40 Gb/s fiber-optic application [C]//ISSCC . San Francisco, CA, USA, 2000: 64-65.
[5] Xu Yang, Feng Jun.Design of 10 Gbit/s demultiplexer in 0.18 μm CMOS [J].Electronic Engineer, 2004, 33(3):5-6.(in Chinese)
[6] Wong Joseph M C, Cheung Vincent S L, Luong Howard C.A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-um CMOS process[J].IEEE Journal of Solid-State Circuits, 2003, 38(10):1643-1648.
[7] Runge K.5 Gbit/s 2 ∶1 multiplexer fabricated in 0.35 μm CMOS and 3 Gbit/s 1∶2 demultiplexer fabricated in 0.5 μm CMOS technology[J].Electronics Letters, 1999, 35(19):1631-1632.

Memo

Memo:

Biographies: Jiang Junjie(1981—), female, graduate;Feng Jun(corresponding author), female, professor, fengjun_-seu@seu.edu.cn.

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