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[1] Hu Qingsheng, Wang Zhigong, Zhang Jun, Xiao Jie, et al. Area optimization of parallel Chien search architecturefor Reed-Solomon(255, 239)decoder [J]. Journal of Southeast University (English Edition), 2006, 22 (1): 5-10. [doi:10.3969/j.issn.1003-7985.2006.01.002]
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Area optimization of parallel Chien search architecturefor Reed-Solomon(255, 239)decoder()
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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
22
Issue:
2006 1
Page:
5-10
Research Field:
Electronic Science and Engineering
Publishing date:
2006-03-20

Info

Title:
Area optimization of parallel Chien search architecturefor Reed-Solomon(255, 239)decoder
Author(s):
Hu Qingsheng;  Wang Zhigong;  Zhang Jun;  Xiao Jie
Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
Keywords:
RS decoder;  Chien search circuit;  area optimization;  Galois field multiplier
PACS:
TN722
DOI:
10.3969/j.issn.1003-7985.2006.01.002
Abstract:
A global optimization algorithm(GOA)for parallel Chien search circuit in Reed-Solomon(RS)(255, 239)decoder is presented.By finding out the common modulo 2 additions within groups of Galois field(GF)multipliers and pre-computing the common items, the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area.Different from other local optimization algorithms, the GOA is a global one.When there are more than one maximum matches at a time, the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly.The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately.This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved.

References:

[1] Lee Hanho.High-speed VLSI architecture for parallel Reed-Solomon decoder [J].IEEE Transactions on Very Large Scale Integration (VLSI)Systems, 2003, 11(4):288-294.
[2] Lee Hanho.An area-efficient Euclidean algorithm block for Reed-Solomon decoder [C]//Proc of IEEE Computer Society Annual Symposium on VLSI.Tampa, FL, 2003: 209-210.
[3] Chang Hsie-Chia, Lin Chien-Ching, Lee Chen-Yi.A low-power Reed-Solomon decoder for STM-16 optical communications [C]//Proc of IEEE Asia-Pacific Conference on ASIC.Taipei, 2002: 351-354.
[4] Song L, Parhi K K.Low complexity modified Mastrovito multipliers over finite fields GF(2mm)[C]//Proc of IEEE ISCAS.Orlando, FL, 1999: 508-512.
[5] Zhang T, Parhi K K.Systematic design of original and modified Mastrovito multipliers for general irreducible polynomials [J].IEEE Trans on Computers, 2001, 50(7):734-749.
[6] Zhu Haikun, Shen Bo, Zhang Qianling.Design of a high performance Reed-Solomon decoder with switch box control logic [C]//Proc of the 4th International Conference on ASIC.Shanghai, China, 2001: 452-455.
[7] Chen Yanni, Parhi K K.Small area parallel Chien search architectures for long BCH codes [J].IEEE Transactions on Very Large Scale Integration (VLSI)Systems, 2004, 12(5):545-549.
[8] Paar C.Optimized arithmetic for Reed-Solomon encoders [C]//Proc of IEEE International Symposium on Information Theory.Ulm, Germany, 1997: 250-255.
[9] Hu Qingsheng, Wang Zhigong, Zhang Jun, et al.Low complexity parallel Chien search architecture for RS decoder [C]//Proc of IEEE ISCAS.Kobe, Japan, 2005: 340-343.

Memo

Memo:
Biography: Hu Qingsheng(1964—), female, doctor, associate professor, qshu@seu.edu.cn.
Last Update: 2006-03-20