[1] Yin Qin, Qi Tao, Wu Guanglin, Wu Jianhui, et al. Capacitor self-calibration technique usedin time-interleaved successive approximation ADC [J]. Journal of Southeast University (English Edition), 2006, 22 (2): 164-168. [doi:10.3969/j.issn.1003-7985.2006.02.005]

Copy

Capacitor self-calibration technique usedin time-interleaved successive approximation ADC()

Share：

Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

22

Issue:

2006 2

Page:

164-168

Research Field:

Circuit and System

Publishing date:

2006-06-30

Info

Title:

Capacitor self-calibration technique usedin time-interleaved successive approximation ADC

Author(s):

Yin Qin;  Qi Tao;  Wu Guanglin;  Wu Jianhui

National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China

Keywords:

capacitor self-calibration;  analog-to-digital converter;  successive approximation;  time-interleaved

PACS:

TN432

DOI:

10.3969/j.issn.1003-7985.2006.02.005

Abstract:

A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter(SA-ADC)is presented.This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC by adding an additional clock period. This circuit is used in a 10 bit 32 Msample/s time-interleaved SA-ADC.The chip is implemented with Chart 0.25 μm 2.5 V process and totally occupies an area of 1.4 mm×1.3 mm.After calibration, the simulated signal-to-noise ratio(SNR)is 59.586 1dB and the spurious-free dynamic range(SFDR)is 70.246 dB at 32 MHz.The measured signal-to-noise and distortion ratio(SINAD)is 44.82 dB and the SFDR is 63.760 4 dB when the ADC samples a 5.8 MHz sinusoid wave.

References:

[1] Yuan Jiren, Sevensson Christer.A 10 bit 5 MS/s successive approximation ADC cell used in a 70 MS/s ADC array in 1.2 μm CMOS [J].IEEE Journal of Solid-State Circuits, 1994, 29(8):866-872.
[2] Kurosawa Naoki, Kobayashi Haruo, Maruyama Kaoru, et al.Explicit analysis of channel mismatch effects in time-interleaved ADC systems [J].IEEE Transactions on Circuits and Systems, 2001, 48(3):261-271.
[3] Leger Gildas, Peralias Eduardo J, Rueda Adoracion, et al.Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs [J].IEEE Transactions on Circuits and Systems, 2004, 51(1):140-150.
[4] Tan Khen-Sang.On board self-calibration of analog-to-digital and digital-to-analog converters [P].United States Patent, 4399426.1983-08-16.
[5] Leung Ka Y, Holberg Douglas R, Leung Kafai.Capacitor calibration in SAR converter [P].United States Patent, 6891487.2005-05-10.
[6] Neubauer H, Desel T, Hauer H.A successive approximation A/D converter with 16 bit 200 KS/s in 0.6 μm CMOS using self calibration and low power techniques [A].In:The 8th IEEE International Conference on Electronics, Circuits and Systems.Piscataway, NJ, USA:IEEE, 2001.859-862.
[7] Wagdy Mahmoud Fawzy.Correction of capacitor errors during the conversion cycle of self-calibrating A/D converters [J].IEEE Transactions on Circuits and Systems, 1990, 37(7):1296-1299.
[8] Huang Feipeng, Wang Jingguang, He Jirou, et al.A 10 bit 50 Msample/s 57.6 mW CMOS pipeline A/D converter [J].Chinese Journal of Semiconductors, 2005, 26(11):2230-2235.(in Chinese)

Memo

Memo:

Biographies: Yin Qin(1981—), male, graduate;Wu Jianhui(corresponding author), male, doctor, professor, wjh@seu.edu.cn.

Common functions