[1] He Xiaohu, Hu Qingsheng,. Design of 0.18 μm CMOS programmable frequency dividerbased on standard cells [J]. Journal of Southeast University (English Edition), 2007, 23 (1): 31-34. [doi:10.3969/j.issn.1003-7985.2007.01.007]
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Design of 0.18 μm CMOS programmable frequency dividerbased on standard cells(
)
基于0.18 μm CMOS标准单元的可编程分频器设计
)Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]
- Volumn:
- 23
- Issue:
- 2007 1
- Page:
- 31-34
- Research Field:
- Circuit and System
- Publishing date:
- 2007-03-30
Info
- Title:
- Design of 0.18 μm CMOS programmable frequency dividerbased on standard cells
- 基于0.18 μm CMOS标准单元的可编程分频器设计
- Author(s):
- He Xiaohu, Hu Qingsheng
- Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
- PACS:
- TN453
- DOI:
- 10.3969/j.issn.1003-7985.2007.01.007
- Abstract:
- The design of a programmable frequency divider, which is one of the components of the phase-locked loop(PLL)frequency synthesizer for transmitter and receiver in IEEE 802.11a standard, is investigated.The main steps in very large-scale integration(VLSI)design flow such as logic synthesis, floorplan and placement & routing(P & R)are introduced.By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology.The programmable frequency divider is implemented based on Artisan TSMC(Taiwan Semicoductor Manufacturing Co. Ltd.)0.18 μm CMOS(complementary metal-oxide-semiconductor)standard cells and fabricated.The chip area is 1 360.5 μm2 and can work in the range of 100 to 200 MHz.The measurement results indicate that the design conforms to the frequency division precision.
- 设计实现了一种应用于IEEE 802.11a收发信机的PLL频率综合器中的可编程分频器.介绍了逻辑综合、版图规划、布局布线等VLSI设计流程的关键步骤, 通过将后端信息返标到前端设计工具, 生成自定义线负载模型, 优化了深亚微米工艺下的设计流程.可编程分频器采用Artisan TSMC 0.18 μm CMOS标准单元库设计并流片.芯片内核面积为1 360.5 μm2, 可工作在100~200 MHz的频率范围.测试结果表明芯片能够完成精确的分频比.
References:
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[9] Synopsys, Inc. Design Compiler reference manual.2002.
[10] He Xiaohu, Hu Qingsheng, Xiao Jie.An example of back-end design for ASIC in deep submicron technology [J].China Integrated Circuit, 2006(8):37-42.(in Chinese)
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Memo
- Memo:
- Biographies: He Xiaohu(1981—), male, graduate;Hu Qingsheng(corresponding author), female, doctor, professor, qshu@seu.edu.cn.