[1] Wang Junfeng, Feng Jun, Li Yihui, Yuan Sheng, et al. 11.6-GHz 0.18-μm monolithic CMOS phase-locked loop [J]. Journal of Southeast University (English Edition), 2007, 23 (1): 35-38. [doi:10.3969/j.issn.1003-7985.2007.01.008]

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11.6-GHz 0.18-μm monolithic CMOS phase-locked loop()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

23

Issue:

2007 1

Page:

35-38

Research Field:

Circuit and System

Publishing date:

2007-03-30

Info

Title:

11.6-GHz 0.18-μm monolithic CMOS phase-locked loop

Author(s):

Wang Junfeng;  Feng Jun;  Li Yihui;  Yuan Sheng;  Xiong Mingzhen;  Wang Zhigong;  Hu Qingsheng

Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China

Keywords:

phase-locked loop;  CMOS technology;  high speed

PACS:

TN492

DOI:

10.3969/j.issn.1003-7985.2007.01.008

Abstract:

A design of a 11.6-GHz phase-locked loop(PLL)fabricated in 49-GHz 0.18-μm CMOS(complementary metal-oxide-semiconductor transistor)technology is described.An analog multiplier phase detector(PD), a one-pole passive low pass filter and a three-stage ring oscillator with variable negative-resistance loads build up the monolithic phase-locked loop.The measured rms jitter of output signal via on-wafer testing is 2.2 ps under the stimulation of 2³¹-1 bit-long pseudo random bit sequence(PRBS)at the bit rate of 11.6 GHz.And the tracking range is 250 MHz.The phase noise in the locked condition is measured to be -107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset.The circuit area of the proposed PLL is only 0.47 mm×0.72 mm and the direct current(DC)power dissipation is 164 mW under a 1.8-V supply.

References:

[1] Wang Zhigong.Design of optical communication integrated circuits [M].Beijing:Higher Education Press, 2003.(in Chinese)
[2] Razavi Behzad.Design of analog CMOS integrated circuits [M].Translated by Chen Guican.Xi’an:Xi’an Jiaotong University Press, 2003.(in Chinese)
[3] Lee Thomas.The design of CMOS radio-frequency integrated circuits [M].Cambirdge:Cambridge University Press, 1998.
[4] Savoj Jafar, Razavi Behzad.A 10 Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector [J].IEEE Journal of Solid-State Circuits, 2001, 36(5):761-767.
[5] Anand Seema Butala, Razavi Behzad.A CMOS clock recovery circuit for 2.5-Gb/s NRZ Data [J].IEEE Journal of Solid-State Circuits, 2001, 36(3):432-439.
[6] Gilbert Barrie.A precise four-quadrant multiplier with subnanosecond response [J].IEEE Journal of Solid-State Circuits, 1968, 3(4):365-373.
[7] Soliman S, Yuan F, Raahemifar K.An overview of design techniques for CMOS phase detectors [C]//IEEE International Symposium on Circuits and Systems.Scottsdale, USA, 2002:457-460.
[8] Best Roland E.Phase-locked loops design, simulation, and applications [M].Beijing:Tsinghua University Press, 2003.
[9] Feng Jun, Jin Jie.Research for high-speed circuit design and library model application [J].Journal of Circuits and Systems, 2005, 10(4):125-127.
[10] Hastings Alan.The art of analog layout [M].Beijing:Tsinghua University Press, 2004.

Memo

Memo:

Biographies: Wang Junfeng(1980—), male, graduate;Feng Jun(corresponding author), female, professor, fengjun_-seu@seu.edu.cn.

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