[1] Zhou Jianzheng, Wang Zhigong,. Robust CMOS phase frequency detectorfor high speed and low jitter charge pump PLL [J]. Journal of Southeast University (English Edition), 2008, 24 (1): 15-19. [doi:10.3969/j.issn.1003-7985.2008.01.004]

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Robust CMOS phase frequency detectorfor high speed and low jitter charge pump PLL()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

24

Issue:

2008 1

Page:

15-19

Research Field:

Electronic Science and Engineering

Publishing date:

2008-03-30

Info

Title:

Robust CMOS phase frequency detectorfor high speed and low jitter charge pump PLL

Author(s):

Zhou Jianzheng¹;  2;  Wang Zhigong¹

¹Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
²School of Computer and Information, Hefei University of Technology, Hefei 230009, China

Keywords:

phase frequency detectors;  dead-zone;  blind-zone;  phase characteristic;  frequency characteristic

PACS:

TN763

DOI:

10.3969/j.issn.1003-7985.2008.01.004

Abstract:

In order to improve the performance of the existing phase frequency detectors(PFDs), a systematical analysis of the existing PFDs is presented.Based on the circuit architecture, both classifications and comparisons are made.A new robust CMOS phase frequency detector for a high speed and low jitter charge pump phrase-locked loop(PLL)is designed.The proposed PFD consists of two rising-edge triggered dynamic D flip-flops, two positive-edge detectors and delaying units and two OR gates. It adopts two reset mechanisms to avoid the UP and DN signals to be logic-1 simultaneously.Thus, any current mismatch of the charge pump circuit will not worsen the performance of the PLL.Furthermore, it has hardly any dead-zone phenomenon in phase characteristic.Simulations with ADS are performed based on a TSMC 0.18-μm CMOS process with a 1.8-V supply voltage.According to the theoretical analyses and simulation results, the proposed PFD shows a satisfactory performance with a high operation frequency(≈1 GHz), a wide phase-detection range [±2π], a near zero dead-zone(<0.1 ps), high reliability, low phase jitter, low power consumption(≈100 μW)and small circuit complexity.

References:

[1] Best R E.Phase-locked loops:design, simulation and applications [M].4th ed. New York:McGraw-Hill, 1999:7-100.
[2] Jeon Sang O, Cheung Tae Sik, Choi W Y.Phase/frequency detectors for high-speed PLL applications [J].Electronics Letters, 1998, 34(22):2120-2121.
[3] Cheng K H, Yao T H, Jiang S Y, et al.A difference detector PFD for low jitter PLL [C]//Proc of ICECS.Malta, 2001, 1:43-46.
[4] Liu R F, Li Y M, Chen H Y.A fully symmetrical PFD for fast locking low jitter PLL [C]//Proc of the 5th International Conference on ASIC.Beijing, China, 2003, 2:725-727.
[5] Chou C P, Lin Z M, Chen J D.A 3-ps dead-zone double-edge-checking phase-frequency-detector with 4.78 GHz operating frequencies [C]//Proc of APCCAS.Tainan, China, 2004, 2:937-940.
[6] Lee W H, Cho J D, Lee S D.A high speed and low power phase-frequency detector and charge-pump [C]//Proc of ASP-DAC’99.Hong Kong, China, 1999, 1:269-272.
[7] Mansuri M, Liu D, Yang C K K.Fast frequency acquisition phase-frequency detectors for G samples/s phase-locked loops [J].IEEE Journal of Solid-State Circuits, 2002, 37(10):1331-1334.
[8] Yoshizawa Hiroyasu, Taniguchi Kenji, Nakashi Kenichi.Phase detectors/phase frequency detectors for high performance PLLs [J].Analog Integrated Circuits and Signal Processing, 2002, 30(3):217-226.
[9] Chang R C, Kuo L C.A differential type CMOS phase frequency detector [C]//Proc of AP-ASIC.Cheju, Korea, 2000:61-64.
[10] Chow H C, Yeh N L.A new phase-locked loop with high speed phase frequency detector [C]//Proc of MWSCAS.Cincinnati, Ohio, USA, 2005, 2:1342-1345.
[11] Kondoh H, Notani H, Yoshimura T, et al.A 1.5 V 250 MHz to 3.0 V 622 MHz operation CMOS phase-locked loop with precharge type phase-detector [J].IEICE Trans Electron, 1995, 78(4):381-388.
[12] Johansson H O.A simple precharged CMOS phase frequency detector [J].IEEE Journal of Solid-State Circuits, 1998, 33(2):295-299.

Memo

Memo:

Biographies: Zhou Jianzheng(1976—), male, graduate, lecturer;Wang Zhigong(corresponding author), male, doctor, professor, zgwang@seu.edu.cn.
Citation: Zhou Jianzheng, Wang Zhigong.Robust CMOS phase frequency detector for high speed and low jitter charge pump PLL[J].Journal of Southeast University(English Edition), 2008, 24(1):15-19.

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