[1] Jiang Yawei, Li Zhiqun, Shu Haiyong, Hou Ningbing, et al. A 5-GHz frequency synthesizer with constant bandwidthfor low IF ZigBee transceiver applications [J]. Journal of Southeast University (English Edition), 2010, 26 (1): 6-10. [doi:10.3969/j.issn.1003-7985.2010.01002]
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A 5-GHz frequency synthesizer with constant bandwidthfor low IF ZigBee transceiver applications(
)
应用于低中频Zigbee收发机的5-GHz恒定带宽频率综合器
)Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]
- Volumn:
- 26
- Issue:
- 2010 1
- Page:
- 6-10
- Research Field:
- Electronic Science and Engineering
- Publishing date:
- 2010-03-30
Info
- Title:
- A 5-GHz frequency synthesizer with constant bandwidthfor low IF ZigBee transceiver applications
- 应用于低中频Zigbee收发机的5-GHz恒定带宽频率综合器
- Author(s):
- Jiang Yawei; Li Zhiqun; Shu Haiyong; Hou Ningbing
- Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
- Keywords:
- phase-locked loop; phase noise; auto frequency calibration; ZigBee; voltage controlled oscillator
- PACS:
- TN742;TN752
- DOI:
- 10.3969/j.issn.1003-7985.2010.01002
- Abstract:
- A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency(IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator(VCO)are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature(IQ)signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency(RF)complementary metal oxide semiconductor transistor(CMOS)technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier, respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs.
- 设计并实现了一个应用于ZigBee收发机的全集成整数N频率综合器.频率综合器中采用了稳定环路带宽技术, 使频率综合器的环路带宽在压控振荡器(VCO)的整个输出频率范围内恒定不变, 从而维持了频率综合器的相位噪声最优值与环路稳定性.频率综合器的同相与正交信号(IQ)由VCO输出端的除2分频器产生.该频率综合器采用0.18 μm RF CMOS工艺技术制造, 芯片面积约1.7 mm2.频率综合器采用在晶圆测试的方式进行了测试.在1.8 V电源电压下, 频率综合器不包括输出缓冲所消耗的总功率为28.8 mW.频率综合器在2.405 GHz载波1及3 MHz频偏处测得相位噪声分别为-110和-122 dBc/Hz.频率综合器在2 MHz频偏处测得的参考杂散为-48.2 dBc.测得的建立时间约为160 μs.
References:
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Memo
- Memo:
-
Biographies: Jiang Yawei(1980—), male, graduate;Li Zhiqun(corresponding author), male, doctor, professor, zhiqunli@seu.edu.cn.
Foundation items: The National High Technology Research and Development Program of China(863 Program)(No.2007AA01Z2A7), the Science and Technology Program of Zhejiang Province(No.2008C16017).
Citation: Jiang Yawei, Li Zhiqun, Shu Haiyong, et al.A 5-GHz frequency synthesizer with constant bandwidth for low IF ZigBee transceiver applications[J].Journal of Southeast University(English Edition), 2010, 26(1):6-10.