[1] Li Bing, Xia Kewei, Liang Wenli,. Reconfigurable implementation of AES algorithm IP corebased on pipeline structure [J]. Journal of Southeast University (English Edition), 2010, 26 (1): 21-25. [doi:10.3969/j.issn.1003-7985.2010.01005]
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Reconfigurable implementation of AES algorithm IP corebased on pipeline structure(
)
基于流水线结构的可重构AES算法IP核的硬件实现
)Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]
- Volumn:
- 26
- Issue:
- 2010 1
- Page:
- 21-25
- Research Field:
- Information and Communication Engineering
- Publishing date:
- 2010-03-30
Info
- Title:
- Reconfigurable implementation of AES algorithm IP corebased on pipeline structure
- 基于流水线结构的可重构AES算法IP核的硬件实现
- Author(s):
- Li Bing, Xia Kewei, Liang Wenli
- School of Integrated Circuits, Southeast University, Nanjing 210096, China
- Keywords:
- advanced encryption standard(AES)algorithm; reconfigurable; pipeline; finite field; round transformation
- PACS:
- TN911.21
- DOI:
- 10.3969/j.issn.1003-7985.2010.01005
- Abstract:
- In order to improve the data throughput of the advanced encryption standard(AES)IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline architecture and reconfigurable technology for the design and implementation of the AES IP core is proposed. The encryption and decryption processes of the AES algorithm are achieved in the same process within the mixed pipeline structure. According to the finite field characterizations, the Sbox in the AES algorithm is optimized. ShiftRow and MixColumn, which are the main components in AES round transformation, are optimized with the reconfigurable technology. The design is implemented on the Xilinx Virtex2p xc2vp20-7 field programmable gate array(FPGA)device. It can achieve a data throughput above 2.58 Gbit/s, and it only requires 3 233 slices. Compared with other related designs of AES IP cores on the same device, the proposed design can achieve a tradeoff between speed and area, and obtain satisfactory results in both data throughput and hardware resource consumption.
- 为了提高AES算法中IP核数据的吞吐量并同时减小硬件资源的占用, 以达到速度和面积的折中实现, 采用混合流水线结构和可重构技术完成了IP核的设计.该设计包括在同一个混合流水线结构的流程中实现了AES算法的加密和解密过程; 根据有限域的性质, 对AES算法中的Sbox盒进行了优化; 结合可重构技术, 完成了对AES轮变换的主要构件ShiftRow和MixColumn的优化. 本设计在Xilinx Virtex2p xc2vp20-7 FPGA器件上完成, 其数据吞吐量达到2.58 Gbit/s, 所需组合逻辑仅为3 233块, 通过与同型号器件上的其他设计进行对比, 实现了速度和面积的折中, 在吞吐量和面积上都得到了比较理想的结果.
References:
[1] Fischer V, Drutarovsky M. Two methods of Rijndael implementation in reconfigurable hardware [C]//The Third International Workshop on Cryptographic Hardware and Embedded Systems. Paris, France, 2001, 2162: 77-92.
[2] National Institute of Standards and Technology(NIST). Advanced encryption standard(AES)(FIPS PUB 197)[S]. Gaithersburg, MD, USA: National Institute of Standards and Technology, 2001.
[3] Daemen J, Rijmen V. The design of Rijndael AES: the advanced encryption standard [M]. Berlin, Germany: Springer-Verlag, 2002.
[4] Sever R, Ismailglu A N, Tekmen Y C, et al. A high speed FPGA implementation of the Rijndael algorithm [C]//Euromicro Symposium on Digital System Design, Architectures, Methods and Tools. Rennes, France, 2004: 358-362.
[5] Sivakumar C, Velmurugan A.high speed VLSI design CCMP AES cipher for WLAN(IEEE 802.11i)[C]//International Conference on Signal Processing, Communications and Networking. Chennai, India, 2007: 398-403.
[6] Hodjat A, Verbauwhede I. A 21.54 Gbits/s fully pipelined AES processor on FPGA [C]//Proceedings of the 12th Annual IEEE Symp on Field-Programmable Custom Computing Machines. Napa, CA, USA, 2004: 308-309.
[7] CAST Inc. AES128-P Programmable advanced encryption standard core [EB/OL].(2005-01-10)[2009-07-10].http: //www.cast-inc.com/cores/aes-p/index.shtml.
[8] Helion Technology Limited Company. High performance AES(Rijndael)cores for Xilinx FPGA[EB/OL].(2005-02-23)[2009-07-10].http: //www.heliontech.com/aes.htm.
Memo
- Memo:
-
Biography: Li Bing(1968—), male, doctor, associate professor, bernie-seu@seu.edu.cn.
Citation: Li Bing, Xia Kewei, Liang Wenli. Reconfigurable implementation of AES algorithm IP core based on pipeline structure[J]. Journal of Southeast University(English Edition), 2010, 26(1): 21-25.