[1] Xu Meng, Wu JianhuiZhang Meng,. Modified Benes network architecture for WiMAX LDPC decoder [J]. Journal of Southeast University (English Edition), 2011, 27 (2): 140-143. [doi:10.3969/j.issn.1003-7985.2011.02.005]

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Modified Benes network architecture for WiMAX LDPC decoder()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

27

Issue:

2011 2

Page:

140-143

Research Field:

Information and Communication Engineering

Publishing date:

2011-06-30

Info

Title:

Modified Benes network architecture for WiMAX LDPC decoder

Author(s):

Xu Meng;  Wu JianhuiZhang Meng

National ASIC System Engineering Research Center, Southeast University, Nanjing 210096

Keywords:

worldwide interoperability for microwave access(WiMAX);  quasi-cycle low density parity check(QC-LDPC);  LDPC decoder;  Benes network

PACS:

TN911.22

DOI:

10.3969/j.issn.1003-7985.2011.02.005

Abstract:

A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access(WiMAX)low density parity check(LDPC)decoders. When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2×2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36.2%.

References:

[1] Gallager R G. Low-density parity check codes [J]. IRE Transactions on Information Theory, 1962, 8(1): 21-28.
[2] MacKay D J C. Good error-correcting codes based on very sparse matrices [J]. IEEE Transactions on Information Theory, 1999, 45(2): 399-431.
[3] Benes V E. Optimal rearrangeable multistage connecting networks [J]. Bell Systems Technology Journal, 1964(43): 1641-1656.
[4] Liew S C, Ng M, Chan C W. Blocking and nonblocking multi-rate Clos switching networks [J]. IEEE/ACM Transactions on Network, 1998, 6(3): 307-318.
[5] Masera G, Quaglio F, Vacca F. Implementation of a flexible LDPC decoder [J]. IEEE Transactions on Circuits and Systems Ⅱ:Express Briefs, 2007, 54(6): 542-546.
[6] Sun Y, Karkooti M, Cavallaro J R. VLSI decoder architecture for high throughput, variable block-size and multi-rate LDPC codes [C]//Proceedings of IEEE International Symposium on Circuits and Systems(ISCAS). New Orleans, USA, 2007:2104-2107.
[7] Tang J, Bhatt T, Sundaramurthy V, et al. Reconfigurable shuffle network design in LDPC decoder [C]//Proceedings of the 17th IEEE International Conference on Application-Specific Systems, Architectures and Processors(ASAP’06). Steamboat Springs, CO, USA, 2006: 81-86.
[8] Oh D, Parhi K K. Low-complexity switch network for reconfigurable LDPC decoders [J]. IEEE Transactions on Very Large Scale Integrated Systems, 2010, 18(1): 85-94.

Memo

Memo:

Biographies: Xu Meng(1982—), male, graduate; Wu Jianhui(corresponding author), male, doctor, professor, wjh@seu.edu.cn.
Foundation item: The National Natural Science Foundation of China(No.60871079).
Citation: Xu Meng, Wu Jianhui, Zhang Meng. Modified Benes network architecture for WiMAX LDPC decoder[J].Journal of Southeast University(English Edition), 2011, 27(2):140-143.[doi:10.3969/j.issn.1003-7985.2011.02.005]

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