[1] Xu Meng, Wu JianhuiZhang Meng,. Modified Benes network architecture for WiMAX LDPC decoder [J]. Journal of Southeast University (English Edition), 2011, 27 (2): 140-143. [doi:10.3969/j.issn.1003-7985.2011.02.005]

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Modified Benes network architecture for WiMAX LDPC decoder()

一种用于WiMAX系统中LDPC译码器的改进型Benes网络结构

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

27

Issue:

2011 2

Page:

140-143

Research Field:

Information and Communication Engineering

Publishing date:

2011-06-30

Info

Title:

Modified Benes network architecture for WiMAX LDPC decoder

一种用于WiMAX系统中LDPC译码器的改进型Benes网络结构

Author(s):

Xu Meng, Wu JianhuiZhang Meng

National ASIC System Engineering Research Center, Southeast University, Nanjing 210096

徐勐, 吴建辉, 张萌

东南大学国家专用集成电路系统工程技术研究中心, 南京 210096

Keywords:

worldwide interoperability for microwave access(WiMAX);  quasi-cycle low density parity check(QC-LDPC);  LDPC decoder;  Benes network

全球互通微波存取(WiMAX);  准循环低密度奇偶校验码;  低密度奇偶校验码译码器;  Benes网络

PACS:

TN911.22

DOI:

10.3969/j.issn.1003-7985.2011.02.005

Abstract:

A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access(WiMAX)low density parity check(LDPC)decoders. When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2×2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36.2%.

提出了一种性能优化的Benes网络结构作为开关网络用于WiMAX 系统中的低密度奇偶校验码译码器.该网络结构在译码器的输入数目不是2的指数时, 能获得最优化的性能.该网络结构是非阻塞的并且可以实现输入输出之间的任何排列组合, 因此可以支持WiMAX系统中规定的19种模式.为了减少网络结构的硬件复杂度, 提出一种用来产生该网络中所有2×2开关的控制信号的高效算法.同时, 使用该高效算法可以减少整个网络的延时.结果表明, 该控制信号的生成电路可以节省25.4%的芯片面积, 并且总体网络的延时可以缩短36.2%.

References:

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[3] Benes V E. Optimal rearrangeable multistage connecting networks [J]. Bell Systems Technology Journal, 1964(43): 1641-1656.
[4] Liew S C, Ng M, Chan C W. Blocking and nonblocking multi-rate Clos switching networks [J]. IEEE/ACM Transactions on Network, 1998, 6(3): 307-318.
[5] Masera G, Quaglio F, Vacca F. Implementation of a flexible LDPC decoder [J]. IEEE Transactions on Circuits and Systems Ⅱ:Express Briefs, 2007, 54(6): 542-546.
[6] Sun Y, Karkooti M, Cavallaro J R. VLSI decoder architecture for high throughput, variable block-size and multi-rate LDPC codes [C]//Proceedings of IEEE International Symposium on Circuits and Systems(ISCAS). New Orleans, USA, 2007:2104-2107.
[7] Tang J, Bhatt T, Sundaramurthy V, et al. Reconfigurable shuffle network design in LDPC decoder [C]//Proceedings of the 17th IEEE International Conference on Application-Specific Systems, Architectures and Processors(ASAP’06). Steamboat Springs, CO, USA, 2006: 81-86.
[8] Oh D, Parhi K K. Low-complexity switch network for reconfigurable LDPC decoders [J]. IEEE Transactions on Very Large Scale Integrated Systems, 2010, 18(1): 85-94.

Memo

Memo:

Biographies: Xu Meng(1982—), male, graduate; Wu Jianhui(corresponding author), male, doctor, professor, wjh@seu.edu.cn.
Foundation item: The National Natural Science Foundation of China(No.60871079).
Citation: Xu Meng, Wu Jianhui, Zhang Meng. Modified Benes network architecture for WiMAX LDPC decoder[J].Journal of Southeast University(English Edition), 2011, 27(2):140-143.[doi:10.3969/j.issn.1003-7985.2011.02.005]

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