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[1] Wang Gang, Wang Qing, Li Bing, et al. High-performance multi-transform architecture for H.264/AVC [J]. Journal of Southeast University (English Edition), 2013, 29 (3): 276-281. [doi:10.3969/j.issn.1003-7985.2013.03.009]
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High-performance multi-transform architecture for H.264/AVC()
一种用于H.264/AVC的高性能多变换结构
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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:
29
Issue:
2013 3
Page:
276-281
Research Field:
Computer Science and Engineering
Publishing date:
2013-09-20

Info

Title:
High-performance multi-transform architecture for H.264/AVC
一种用于H.264/AVC的高性能多变换结构
Author(s):
Wang Gang1;  2;  Wang Qing1;  Li Bing2;  Chen Rui3
1 School of Instrument Science and Engineering, Southeast University, Nanjing 210096, China
2 Wuxi Branch, Southeast University, Wuxi 214135, China
3 Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China
王刚1;  2;  王庆1;  李冰2;  陈锐3
1东南大学仪器科学与工程学院, 南京 210096; 2东南大学无锡分校, 无锡 214135; 3中国科学院电子学研究所, 北京 100190
Keywords:
H.264/AVC;  multi-transform architecture;  Hadamard transform;  integer transform
H.264/AVC;  多变换结构;  哈达码变换;  整数变换
PACS:
TP302
DOI:
10.3969/j.issn.1003-7985.2013.03.009
Abstract:
In order to increase the hardware utilization and minimize the chip area, a multi-transform coding architecture which includes 4×4 forward integer transform, 4×4 inverse integer transform, 4×4 Hadamard transform and 2×2 Hadamard transform is proposed. By simplifying these transforms and exploring their similarities, the proposed design merges the architectures, processing individual transforms into a high-performance multi-transform coding architecture. Using a semiconductor manufacturing international corporation(SMIC)0.18 μm complementary metal oxide semiconductor(CMOS)technology, the proposed architecture achieves the maximum operating clock frequency of 200 MHz and the throughput rate of 800×106 pixel/s with the hardware cost of 3 704 gates. The results demonstrate that the data throughput rate per unit area(DTUA)of this design is at least 40.28% higher than that of the reference design. This design can meet the requirements of real-time decoding digital cinema video(4 096×2 048@30 Hz)at 62.9 MHz, which helps to reduce the power consumption.
为了提高硬件使用率、减少芯片面积, 提出了一种包括4×4正反变换、4×4 哈达码变换及2×2 哈达码变换在内的多变换编码结构.通过将这几种变换算法化简, 并且研究它们之间的相似性, 将处理单个变换的结构合并成一个高性能多变换编码结构.采用SMIC 0.18 μm CMOS工艺, 该结构最高工作频率可达200 MHz, 并在消耗3704门电路的情况下, 达到800×106 pixel/s的吞吐率.结果表明, 该设计的吞吐率和电路规模的比值DTUA比参考设计至少提高了40.28%, 并且在62.9 MHz的频率下支持分辨率为4 096×2 048、刷新频率为30 Hz的视频实时解码需求, 从而有助于降低功耗.

References:

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Memo

Memo:
Biographies: Wang Gang(1977—), male, graduate; Wang Qing(corresponding author), male, doctor, professor, w3398@263. net.
Foundation item: The National Key Technology R& D Program of China during the 12th Five Year Plan Period(No.2013BAJ05B03).
Citation: Wang Gang, Wang Qing, Li Bing, et al. High-performance multi-transform architecture for H.264/AVC[J].Journal of Southeast University(English Edition), 2013, 29(3):276-281.[doi:10.3969/j.issn.1003-7985.2013.03.009]
Last Update: 2013-09-20