[1] Agrawal M, Chakrabarty K. Test-cost modeling and optimal test-flow selection of 3D-stacked ICs [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(9):1523-1536.
[2] Agrawal M, Chakrabarty K. Test-cost optimization and test-flow selection for 3D-stacked ICs [C]//2013 IEEE 31st VLSI Test Symposium (VTS). Berkeley, CA, USA, 2013:1-6. DOI:10.1109/vts.2013.6548941.
[3] Taouil M, Hamdioui S. Test impact on the overall die-to-wafer 3D stacked IC cost [J]. Journal of Electronic Testing, 2012, 28(1):15-25.
[4] Taouil M, Hamdioui S. Stacking order impact on overall 3D die-to-wafer stacked-IC cost [C]// IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Cottbus, Germany, 2011:335-340.
[5] Liang H G, Chang H. Optimized mid-bond order for 3D stacked ICs considering failed bonding [J]. Chinese Journal of Electronics, 2015, 24(2):223-228. DOI:10.1049/cje.2015.04.001. (in Chinese)
[6] Koren I, Koren Z. Defect tolerance in VLSI circuits: Techniques and yield analysis [J]. Proceedings of the IEEE, 1998, 86(9):1819-1838. DOI:10.1109/5.705525.
[7] Chen Y, Niu D, Xie Y.Cost-effective integration of three-dimensional ICs emphasizing testing cost analysis [C]// IEEE International Conference on Computer-Aided Design. San Jose, CA, USA, 2010: 471-476.
[8] Deng Y D, Maly W P. 2.5-dimensional VLSI system integration [J]. IEEE Transactions on Very Large Scale Integration Systems, 2005, 13(6):668–677.
[9] Krishnendu C. ITC’02 SOC test benchmarks [EB/OL].(2008-08-22)[2017-05-20]. http://itc02socbenchm.pratt.duke.edu.
[10] Hsu C Y, Kuo C Y, et al. 3D IC test scheduling using simulated annealing [C]// International Symposium on VLSI Design, Automation, and Test. Hsinchu, China, 2012:1-4.
[11] Jiang L, Xu Q. Yield and reliability enhancement for 3D ICs: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist [C]// IEEE International Test Conference. Anaheim, CA, USA, 2015:1-11. DOI:10.1109/test.2015.7342423.
[12] Cadix L. Lifting the veil on silicon interposer pricing [EB/OL].(2012-12)[2017-05-20]. http://electroiq.com/blog/articles/2012/12/lifting-the-veil-on-silicon-interposer-pricing/.
[13] Wang R, Chakrabarty K, Bhawmik S. Interconnect testing and test-path scheduling for interposer-based 2.5-D ICs [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(1):136-149.DOI: 10.1109/TCAD.2014.2365097.