[1] Wang Gang, Wang Qing, Li Bing, et al. High-performance multi-transform architecture for H.264/AVC [J]. Journal of Southeast University (English Edition), 2013, 29 (3): 276-281. [doi:10.3969/j.issn.1003-7985.2013.03.009]

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High-performance multi-transform architecture for H.264/AVC()

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Journal of Southeast University (English Edition)[ISSN:1003-7985/CN:32-1325/N]

Volumn:

29

Issue:

2013 3

Page:

276-281

Research Field:

Computer Science and Engineering

Publishing date:

2013-09-20

Info

Title:

High-performance multi-transform architecture for H.264/AVC

Author(s):

Wang Gang¹;  2;  Wang Qing¹;  Li Bing²;  Chen Rui³

¹ School of Instrument Science and Engineering, Southeast University, Nanjing 210096, China
² Wuxi Branch, Southeast University, Wuxi 214135, China
³ Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China

Keywords:

H.264/AVC;  multi-transform architecture;  Hadamard transform;  integer transform

PACS:

TP302

DOI:

10.3969/j.issn.1003-7985.2013.03.009

Abstract:

In order to increase the hardware utilization and minimize the chip area, a multi-transform coding architecture which includes 4×4 forward integer transform, 4×4 inverse integer transform, 4×4 Hadamard transform and 2×2 Hadamard transform is proposed. By simplifying these transforms and exploring their similarities, the proposed design merges the architectures, processing individual transforms into a high-performance multi-transform coding architecture. Using a semiconductor manufacturing international corporation(SMIC)0.18 μm complementary metal oxide semiconductor(CMOS)technology, the proposed architecture achieves the maximum operating clock frequency of 200 MHz and the throughput rate of 800×10⁶ pixel/s with the hardware cost of 3 704 gates. The results demonstrate that the data throughput rate per unit area(DTUA)of this design is at least 40.28% higher than that of the reference design. This design can meet the requirements of real-time decoding digital cinema video(4 096×2 048@30 Hz)at 62.9 MHz, which helps to reduce the power consumption.

References:

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[2] Rubin G. Parallel 4×4 transform on bit serial shared memory architecture for H.264/AVC [C]//Proc of the 16th International Conference on Mixed Design of Integrated Circuits & Systems. Lodz, Poland, 2009:675-680.
[3] Porto R, Bampi M, Agostini S, et al. High throughput architecture for forward transforms of H.264/AVC video coding standard [C]//Proc of the 14th IEEE International Conference on Electronics, Circuits and Systems. Marrakech, Morocco, 2007:150-153.
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[9] Hwangbo W, Kim J, Kyung C M. A high-performance 2-D inverse transform architecture for the H.264/AVC decoder[C]//Proc of IEEE International Symposium on Circuits and Systems. New Orleans, LA, USA, 2007:1613-1616.
[10] Hwangbo W, Kyung C M. A multi-transform architecture for H.264/AVC high-profile coders [J]. IEEE Transactions on Multimedia, 2010, 12(3):157-167.
[11] Wang K W, Chen J L, Cao W, et al. A reconfigurable multi-transform VLSI architecture supporting video codec design[J]. IEEE Transactions on Circuits and Systems Ⅱ, 2011, 58(7):432-436.
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Memo

Memo:

Biographies: Wang Gang(1977—), male, graduate; Wang Qing(corresponding author), male, doctor, professor, w3398@263. net.
Foundation item: The National Key Technology R& D Program of China during the 12th Five Year Plan Period(No.2013BAJ05B03).
Citation: Wang Gang, Wang Qing, Li Bing, et al. High-performance multi-transform architecture for H.264/AVC[J].Journal of Southeast University(English Edition), 2013, 29(3):276-281.[doi:10.3969/j.issn.1003-7985.2013.03.009]

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